Competitive internship stipend * Mentorship from a team of researchers and engineers from Anthropic, DeepMind, Meta, and Stanford * Opportunity to work on 0 to 1 problems in AI‑driven chip design ...
Competitive internship stipend * Mentorship from a team of researchers and engineers from Anthropic, DeepMind, Meta, and Stanford * Opportunity to work on 0 to 1 problems in AI‑driven chip design ...
CAD Engineer - Signoff Infrastructure
Austin, TX · On-site
$129K - $194K/yr
Preferred Qualifications Coursework or projects in web development or databases Interest in chip design, VLSI, or CAD tools Interest in AI/ML technologies Personal projects or internships involving ...
CAD Engineer - Signoff Infrastructure
Austin, TX · On-site
$129K - $194K/yr
Preferred Qualifications Coursework or projects in web development or databases Interest in chip design, VLSI, or CAD tools Interest in AI/ML technologies Personal projects or internships involving ...
CAD Engineer - Signoff Infrastructure
Austin, TX · On-site
$129K - $194K/yr
Preferred Qualifications Coursework or projects in web development or databases Interest in chip design, VLSI, or CAD tools Interest in AI/ML technologies Personal projects or internships involving ...
CAD Engineer - Signoff Infrastructure
Austin, TX · On-site
$129K - $194K/yr
Preferred Qualifications Coursework or projects in web development or databases Interest in chip design, VLSI, or CAD tools Interest in AI/ML technologies Personal projects or internships involving ...
AI Research Intern
Mountain View, CA · On-site
... interns with significant experience with AI research (across models, algorithms, and training methodology) to help push the frontier of our AI-native tools and agent-driven workflows for chip design.
AI Research Intern
Mountain View, CA · On-site
... interns with significant experience with AI research (across models, algorithms, and training methodology) to help push the frontier of our AI-native tools and agent-driven workflows for chip design.
SoC Physical Design Engineer, PnR
Austin, TX · On-site
$134K - $138K/yr
... chip design flow, physical synthesis, floor-planning, place and route (PnR), power grid, timing ... Previous internship/co-op, project work or relevant coursework in computer architecture, VLSI ...
SoC Physical Design Engineer, PnR
Austin, TX · On-site
$134K - $138K/yr
... chip design flow, physical synthesis, floor-planning, place and route (PnR), power grid, timing ... Previous internship/co-op, project work or relevant coursework in computer architecture, VLSI ...
$100K - $103K/yr
... chip design flow, physical synthesis, floor-planning, place and route (PnR), power grid, timing ... Previous internship/co-op, project work or relevant coursework in computer architecture, VLSI ...
$100K - $103K/yr
... chip design flow, physical synthesis, floor-planning, place and route (PnR), power grid, timing ... Previous internship/co-op, project work or relevant coursework in computer architecture, VLSI ...
Analog IC Layout Engineer
South San Francisco, CA · On-site
$83K - $139K/yr
... chip design with advanced architectures and hardware accelerators with a goal of enhancing the ... Temporary Employees & Interns excluded
Analog IC Layout Engineer
South San Francisco, CA · On-site
$83K - $139K/yr
... chip design with advanced architectures and hardware accelerators with a goal of enhancing the ... Temporary Employees & Interns excluded
Spring 2027 Silicon Engineering Internship/Co-op
Redmond, WA · On-site
$40/hr
... chip design and development, you are a great candidate! Aerospace experience is not required to be ... Internships are available with a variety of silicon engineering teams across the company at Irvine ...
Spring 2027 Silicon Engineering Internship/Co-op
Redmond, WA · On-site
$40/hr
... chip design and development, you are a great candidate! Aerospace experience is not required to be ... Internships are available with a variety of silicon engineering teams across the company at Irvine ...
Spring 2027 Silicon Engineering Internship/Co-op
Palo Alto, CA · On-site
$40/hr
... chip design and development, you are a great candidate! Aerospace experience is not required to be ... Internships are available with a variety of silicon engineering teams across the company at Irvine ...
Spring 2027 Silicon Engineering Internship/Co-op
Palo Alto, CA · On-site
$40/hr
... chip design and development, you are a great candidate! Aerospace experience is not required to be ... Internships are available with a variety of silicon engineering teams across the company at Irvine ...
... chip design and development, you are a great candidate! Aerospace experience is not required to be ... Internships are available with a variety of silicon engineering teams across the company at Irvine ...
... chip design and development, you are a great candidate! Aerospace experience is not required to be ... Internships are available with a variety of silicon engineering teams across the company at Irvine ...
... chip design and development, you are a great candidate! Aerospace experience is not required to be ... Internships are available with a variety of silicon engineering teams across the company at Irvine ...
... chip design and development, you are a great candidate! Aerospace experience is not required to be ... Internships are available with a variety of silicon engineering teams across the company at Irvine ...
$40/hr
... chip design and development, you are a great candidate! Aerospace experience is not required to be ... Internships are available with a variety of silicon engineering teams across the company at Irvine ...
$40/hr
... chip design and development, you are a great candidate! Aerospace experience is not required to be ... Internships are available with a variety of silicon engineering teams across the company at Irvine ...
Summer 2027 Silicon Engineering Internship/Co-op
Irvine, CA · On-site
$40/hr
... chip design and development, you are a great candidate! Aerospace experience is not required to be ... Internships are available with a variety of silicon engineering teams across the company at Irvine ...
Summer 2027 Silicon Engineering Internship/Co-op
Irvine, CA · On-site
$40/hr
... chip design and development, you are a great candidate! Aerospace experience is not required to be ... Internships are available with a variety of silicon engineering teams across the company at Irvine ...
... chip design and development, you are a great candidate! Aerospace experience is not required to be ... Internships are available with a variety of silicon engineering teams across the company at Irvine ...
... chip design and development, you are a great candidate! Aerospace experience is not required to be ... Internships are available with a variety of silicon engineering teams across the company at Irvine ...
$40/hr
... chip design and development, you are a great candidate! Aerospace experience is not required to be ... Internships are available with a variety of silicon engineering teams across the company at Irvine ...
$40/hr
... chip design and development, you are a great candidate! Aerospace experience is not required to be ... Internships are available with a variety of silicon engineering teams across the company at Irvine ...
Spring 2027 Silicon Engineering Internship/Co-op
Irvine, CA · On-site
$40/hr
... chip design and development, you are a great candidate! Aerospace experience is not required to be ... Internships are available with a variety of silicon engineering teams across the company at Irvine ...
Spring 2027 Silicon Engineering Internship/Co-op
Irvine, CA · On-site
$40/hr
... chip design and development, you are a great candidate! Aerospace experience is not required to be ... Internships are available with a variety of silicon engineering teams across the company at Irvine ...
... chip design and development, you are a great candidate! Aerospace experience is not required to be ... Internships are available with a variety of silicon engineering teams across the company at Irvine ...
... chip design and development, you are a great candidate! Aerospace experience is not required to be ... Internships are available with a variety of silicon engineering teams across the company at Irvine ...
Summer 2027 Silicon Engineering Internship/Co-op
Palo Alto, CA · On-site
$40/hr
... chip design and development, you are a great candidate! Aerospace experience is not required to be ... Internships are available with a variety of silicon engineering teams across the company at Irvine ...
Summer 2027 Silicon Engineering Internship/Co-op
Palo Alto, CA · On-site
$40/hr
... chip design and development, you are a great candidate! Aerospace experience is not required to be ... Internships are available with a variety of silicon engineering teams across the company at Irvine ...
... chip design and development, you are a great candidate! Aerospace experience is not required to be ... Internships are available with a variety of silicon engineering teams across the company at Irvine ...
... chip design and development, you are a great candidate! Aerospace experience is not required to be ... Internships are available with a variety of silicon engineering teams across the company at Irvine ...
$40/hr
... chip design and development, you are a great candidate! Aerospace experience is not required to be ... Internships are available with a variety of silicon engineering teams across the company at Irvine ...
$40/hr
... chip design and development, you are a great candidate! Aerospace experience is not required to be ... Internships are available with a variety of silicon engineering teams across the company at Irvine ...
Internship Chip Design information
See salary details
$9.13 - $11.65
9% of jobs
$11.65 - $14.16
8% of jobs
$14.81 is the 25th percentile. Wages below this are outliers.
$14.16 - $16.67
28% of jobs
The median wage is $17.34 / hr.
$16.67 - $19.19
16% of jobs
$20.91 is the 75th percentile. Wages above this are outliers.
$19.19 - $21.70
20% of jobs
$21.70 - $24.21
9% of jobs
$24.21 - $26.73
4% of jobs
$26.73 - $29.24
1% of jobs
$29.24 - $31.75
1% of jobs
$31.75 - $34.27
1% of jobs
$34.27 - $36.78
2% of jobs
$9
$19
$36
How much do internship chip design jobs pay per hour?
What is an internship in chip design?
What types of projects and responsibilities can I expect during an internship in chip design?
What are the key skills and qualifications needed to thrive as an internship chip design, and why are they important?
What is the difference between Internship Chip Design vs Chip Design Engineer?
| Aspect | Internship Chip Design | Chip Design Engineer |
|---|---|---|
| Required Credentials | Enrolled in or recent graduate of Electrical Engineering or related field | Bachelor's or Master's in Electrical Engineering, Computer Engineering, or related |
| Work Environment | Internship programs, team projects, supervised tasks | Full-time professional setting, independent project work |
| Employer & Industry Usage | Internship positions in semiconductor and electronics companies | Full-time roles in chip design companies, tech firms, or semiconductor industry |
| Comparison Search Intent | Learning about entry-level opportunities and training | Understanding professional career roles and responsibilities |
Internship Chip Design positions are entry-level opportunities aimed at students or recent graduates, focusing on training and skill development under supervision. Chip Design Engineers are full-time professionals responsible for designing, testing, and implementing integrated circuits independently. While internships provide foundational experience, engineers hold advanced responsibilities in the industry.
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Cities with the most Internship Chip Design job openings:
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States with the most job openings for Internship Chip Design jobs include:
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The top searched job categories for Internship Chip Design jobs are:

Member of Technical Staff - Research Intern
Palo Alto, CA • On-site
Other
Re-posted 18 days ago
Job description
About Architect
Architect is an AI research and product lab for chip design. We build AI models and systems that can explore, design, optimize, and verify new hardware. Our goal is to reimagine chip design using AI, cut down ASIC design time and cost, and enable a new era of ultra‑efficient, domain‑specific chips powering the future of computation.
Born out of Stanford, our team blends researchers and engineers from Anthropic, DeepMind, Meta, Apple, Intel, and other frontier labs. Backed by leading VCs and angels, including the Chief Scientist at Google, Stanford professors, and founders of chip companies, Architect operates in stealth, pushing the limits of AI4EDA and building the intelligence layer for the hardware revolution.
What You’ll DoAs a Research Intern at Architect, you will spend 3 months working alongside the founding team to push the boundaries of how AI models explore and optimize hardware designs. This is a high‑impact role where your experiments will directly influence our core modeling roadmap.
- Responsible for co‑designing and implementing the Reinforcement Learning experiments (GRPO/PPO/DPO), training data mixes and reward signal explorations.
- Contribute to research on post‑training techniques, running ablation studies to improve model reasoning and alignment capabilities.
- Implement and test new algorithms for model fine‑tuning and evaluation, helping to translate research papers into working prototypes.
- Analyze experimental results and debug model behavior to help establish best practices for our training recipes.
Qualifications & Skills:
- Education: Currently pursuing a PhD or Master’s degree in Computer Science, Machine Learning, Mathematics, or a related field. Exceptional undergraduates with strong research experience are also encouraged to apply.
- RL Knowledge: Strong academic understanding or project experience with Reinforcement Learning (e.g., PPO, DPO, GRPO). You should be comfortable reading and implementing concepts from recent research papers.
- Coding Proficiency: Strong proficiency in Python and deep learning frameworks (PyTorch). You should be able to write clean, efficient research code.
- Research Mindset: A fast learner who is comfortable navigating ambiguity. You enjoy analyzing complex problems and iterating quickly on experiments.
- LLM Familiarity: Experience with training or fine‑tuning Large Language Models (LLMs) or familiarity with the modern NLP stack (Transformers, HuggingFace, etc.).
- Previous internship experience at frontier AI labs or research organizations.
- Publications (or submissions) in top ML venues (NeurIPS, ICLR, ICML) or EDA venues (DAC, ICCAD).
- Familiarity with hardware design concepts (Verilog, RTL, EDA tools), though not required.
- Competitive internship stipend
- Mentorship from a team of researchers and engineers from Anthropic, DeepMind, Meta, and Stanford
- Opportunity to work on 0 to 1 problems in AI‑driven chip design