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Internship Asic Rtl Design Engineer Jobs in Colorado

SEAKR Engineering

Senior FPGA Engineer

Englewood, CO · On-site

$130K - $185K/yr

Completing multiple FPGA or ASIC design using Verilog and/or VHDL, including at least one of ... FPGA design experience including thorough design documentation, completion and review of RTL blocks ...

Protingent

Verification Engineer

Englewood, CO · On-site

$130K - $200K/yr

Work on both ASIC and FPGA Space system projects Job Qualifications: * 7+ years of relevant design ... RTL Design experience * Experience validating designs for Space Applications Job Details: * Job ...

Lockheed Martin

ASIC/FPGA Design Engineer IV

Littleton, CO · On-site

$124K - $171K/yr

Join Our Team as an ASIC & FPGA Design Engineer where you will support over 50 different programs and research and development (R&D) efforts, affecting technology across military space, civil space ...

Ursa Major

Staff FPGA Design Engineer

Berthoud, CO

$123K - $169K/yr

As a Staff Electrical Engineer, you will work with cross-functional design and development teams to ... Architect and generate ASIC/FPGA RTL code * Generate test cases and run simulations to verify ...

Ursa Major

Staff FPGA Design Engineer

Berthoud, CO · On-site

$123K - $169K/yr

Architect and generate ASIC/FPGA RTL code * Generate test cases and run simulations to verify ... Classification: Full-time Exempt Benefits Include: (Please note, Interns are not eligible for ...

Broadcom

Digital Design RTL Engineer

Fort Collins, CO · On-site

$134K/yr

The ideal candidate has a proven track record of delivering high-quality SystemVerilog RTL in advanced process nodes (5nm and below) and possesses a deep understanding of RTL Design, PPA optimization ...

Ursa Major

Staff FPGA Design Engineer

Berthoud, CO

$123K - $169K/yr

Architect and generate ASIC/FPGA RTL code * Generate test cases and run simulations to verify ... Classification: Full-time Exempt Benefits Include: (Please note, Interns are not eligible for ...

Broadcom, Inc.

Digital Design RTL Engineer

Fort Collins, CO · On-site

$134K/yr

The ideal candidate has a proven track record of delivering high-quality SystemVerilog RTL in advanced process nodes (5nm and below) and possesses a deep understanding of RTL Design, PPA optimization ...

Broadcom, Inc.

Digital Design RTL Engineer

Fort Collins, CO · On-site

$134K/yr

The ideal candidate has a proven track record of delivering high-quality SystemVerilog RTL in advanced process nodes (5nm and below) and possesses a deep understanding of RTL Design, PPA optimization ...

Broadcom

Digital Design RTL Engineer

Fort Collins, CO · On-site

$134K/yr

The ideal candidate has a proven track record of delivering high-quality SystemVerilog RTL in advanced process nodes (5nm and below) and possesses a deep understanding of RTL Design, PPA optimization ...

Broadcom

Digital Design RTL Engineer

Fort Collins, CO · On-site

$134K/yr

The ideal candidate has a proven track record of delivering high-quality SystemVerilog RTL in advanced process nodes (5nm and below) and possesses a deep understanding of RTL Design, PPA optimization ...

Broadcom, Inc.

Digital Design RTL Engineer

Fort Collins, CO · On-site

$134K/yr

The ideal candidate has a proven track record of delivering high-quality SystemVerilog RTL in advanced process nodes (5nm and below) and possesses a deep understanding of RTL Design, PPA optimization ...

Broadcom

IC Design Engineer

Fort Collins, CO · On-site

Broadcom's ASIC Products Division is seeking a Design Automation Software Development Engineer in the Design For Test (DFT) team developing SoC ASIC products. They will define, develop, deploy and ...

Broadcom, Inc.

IC Design Engineer

Fort Collins, CO · On-site

Broadcom's ASIC Products Division is seeking a Design Automation Software Development Engineer in the Design For Test (DFT) team developing SoC ASIC products. They will define, develop, deploy and ...

Broadcom

Design Verification Engineer

Fort Collins, CO · On-site

$134K - $164K/yr

Design Verification Engineer Broadcom's ASIC Products Division (APD), a worldwide leader in the ... The engineer must be knowledgeable of RTL, gate-level netlists, and SDF and capable of analyzing ...

Broadcom

Design Verification Engineer

Broomfield, CO · On-site

$137K - $167K/yr

Design Verification Engineer Broadcom's ASIC Products Division (APD), a worldwide leader in the ... The engineer must be knowledgeable of RTL, gate-level netlists, and SDF and capable of analyzing ...

Broadcom

Physical Design Engineer

Colorado Springs, CO

$134K - $138K/yr

Setup and Synthesizing RTL * Timing closure through various methods and strategies; preferable in ... Collaborating with IC Design RTL Engineers * Must work in person at our Colorado Springs site - no ...

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Internship Asic Rtl Design Engineer information

What does an internship ASIC RTL design engineer do?

As an ASIC RTL Design Engineering intern, you'll typically work on tasks such as writing and verifying RTL code using languages like Verilog or VHDL, assisting with simulation and debugging, and collaborating closely with senior engineers on real design blocks. Interns often participate in design reviews, update documentation, and may get hands-on experience with synthesis and timing analysis tools. This role is highly collaborative and provides exposure to the complete ASIC development cycle, making it an excellent opportunity to build foundational skills and gain insight into industry-standard methodologies.

What are the key skills and qualifications needed to thrive as an internship ASIC RTL design engineer?

To thrive as an Internship ASIC RTL Design Engineer, you need a solid understanding of digital logic design, computer architecture, and proficiency in HDL languages like Verilog or VHDL, typically supported by coursework in electrical or computer engineering. Familiarity with industry-standard EDA tools such as Synopsys, Cadence, or Mentor Graphics, and simulation environments is highly valuable. Strong analytical thinking, attention to detail, and effective communication skills help interns collaborate with teams and learn quickly in a fast-paced environment. These skills and qualities are essential for contributing to complex chip design projects and ensuring accuracy and efficiency in RTL development.

What is an internship ASIC RTL design engineer?

An Internship ASIC RTL (Register Transfer Level) Design Engineer is a student or recent graduate who assists in designing and developing digital integrated circuits (ICs) using hardware description languages like Verilog or VHDL. They work under the guidance of senior engineers to create, simulate, and verify RTL code for ASIC (Application Specific Integrated Circuit) projects. The role provides hands-on experience with the chip design process, including synthesis, timing analysis, and verification. Interns gain valuable exposure to industry-standard tools and methodologies, helping them prepare for a full-time engineering career.

What is the difference between Internship Asic Rtl Design Engineer vs Asic Verification Engineer?

AspectInternship Asic Rtl Design EngineerAsic Verification Engineer
CredentialsTypically pursuing or recently completed a degree in Electrical Engineering or Computer EngineeringSimilar educational background, often with additional coursework in verification methodologies
Work EnvironmentInternship setting, supervised, focused on learning and assisting in RTL design tasksFull-time role, focused on testing and verifying RTL designs
Industry UsageUsed in semiconductor and chip design companies during early career stagesCommon in companies developing complex integrated circuits and chips

The Internship Asic Rtl Design Engineer focuses on assisting in RTL design tasks during an internship, emphasizing learning and support. In contrast, the Asic Verification Engineer is responsible for verifying RTL designs to ensure functionality. Both roles require similar educational backgrounds but differ in responsibilities and work environment, with verification roles being more advanced and permanent.

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Infographic showing various Internship Asic Rtl Design Engineer job openings in Colorado as of August 2026, with employment types broken down into 72% Full Time, and 28% Contract. Highlights an 74% In-person, and 26% Remote job distribution.

Senior FPGA Engineer

SEAKR Engineering

Englewood, CO • On-site

$130K - $185K/yr

Full-time

Medical, Dental, Vision, Retirement, PTO

Re-posted 3 days ago

Job description

Company Description
Join SEAKR Engineering, a leading-edge provider of advanced electronics for space applications. Pushing the boundaries of technology on a mission to change the world for the better from space.
Job Description
Seeking an FPGA Engineer who has extensive knowledge of digital circuit design, state machines, Boolean math and FPGAs.
Candidate shall have experience with
  • Completing multiple FPGA or ASIC design using Verilog and/or VHDL, including at least one of moderate complexity
  • Demonstrate knowledge and development of a test bench with self-checking and simulation (including back annotated timing) for given FPGA modules, top level FPGA, and system with multiple FPGAs
  • FPGA technology differences (Xilinx vs Actel/Microsemi)
  • FPGA process and development flows, especially flows using Synplify Pro, ISE, Vivado and Libero
  • Scripting languages such as TCL or Python
  • Leading small sized teams in order to develop moderately complex systems according to program schedule expectations

Required skills
  • FPGA design experience including thorough design documentation, completion and review of RTL blocks, participation in code reviews, significant RTL debug, and working knowledge of CDC, reset and clock design
  • Ability to solve digital lab debug problems with use of lab tools such as bench supplies, scopes and logic analyzers

Knowledge of RTL design techniques for radiation upset mitigation and experience using multiple RTL languages are a plus.
Qualifications
  • Candidate shall also have leadership skills and ability to provide support and technical direction to junior engineers.
  • Clear written and verbal communication skills are required.
  • A Bachelor's degree in Electrical Engineering or Computer Science is desired.
  • Must have at least 10+ years of FPGA experience.

Additional Information
Compensation: Base pay range is $130,000-185,000 depending on qualifications. SEAKR has very rich medical, dental and vision insurance plans, along with a generous 401(k) retirement plan. In addition to base salary, employees are eligible for a year-end bonus. SEAKR offers a variety of paid leave, such as vacation, sick, bereavement, and FMLA.
SEAKR is an Equal Opportunity Employer - All your information will be kept confidential according to EEO guidelines.
US Citizenship Required
Applications will be accepted until 6/19/26

Apply