FPGA emulation * Analog mixed-signal co-simulation * Design for testability * Collaboration on ... California Hourly Flat Rate: $35/Hr USD
FPGA emulation * Analog mixed-signal co-simulation * Design for testability * Collaboration on ... California Hourly Flat Rate: $35/Hr USD
Digital IC Design Engineer Intern
Fremont, CA · On-site
$35/hr
FPGA emulation * Analog mixed-signal co-simulation * Design for testability * Collaboration on ... California Hourly Flat Rate: $35/Hr USD What We Offer: Full-time employees are eligible for the ...
Digital IC Design Engineer Intern
Fremont, CA · On-site
$35/hr
FPGA emulation * Analog mixed-signal co-simulation * Design for testability * Collaboration on ... California Hourly Flat Rate: $35/Hr USD What We Offer: Full-time employees are eligible for the ...
Hardware Reverse Engineer SME with Security Clearance
Arlington, VA · On-site
$142K - $187K/yr
... with system emulation or virtual hardware analysis platforms Knowledge of adversary tactics ... Hourly employees are not eligible for paid time off unless required by law. Hourly employees on a ...
Hardware Reverse Engineer SME with Security Clearance
Arlington, VA · On-site
$142K - $187K/yr
... with system emulation or virtual hardware analysis platforms Knowledge of adversary tactics ... Hourly employees are not eligible for paid time off unless required by law. Hourly employees on a ...
Senior Digital Validation Engineer
San Diego, CA · On-site
$130K - $179K/yr
Lead validation on presilicon platforms , such as FPGA emulation * Execute and guide postsilicon ... Please note that the base salary range (OR hourly rate) is a guideline, and individual total ...
Senior Digital Validation Engineer
San Diego, CA · On-site
$130K - $179K/yr
Lead validation on presilicon platforms , such as FPGA emulation * Execute and guide postsilicon ... Please note that the base salary range (OR hourly rate) is a guideline, and individual total ...
Senior Digital Validation Engineer
San Diego, CA · On-site
$130K - $179K/yr
Lead validation on pre-silicon platforms , such as FPGA emulation * Execute and guide post-silicon ... Please note that the base salary range (OR hourly rate) is a guideline, and individual total ...
Senior Digital Validation Engineer
San Diego, CA · On-site
$130K - $179K/yr
Lead validation on pre-silicon platforms , such as FPGA emulation * Execute and guide post-silicon ... Please note that the base salary range (OR hourly rate) is a guideline, and individual total ...
Control Applications Tech Intern II
Glendale, WI · On-site
$21 - $24/hr
Pre-Entry level engineering position joining the team that develops Equipment Controls, Building ... Working on small projects that aid in the development, simulation and emulation of our products.
Control Applications Tech Intern II
Glendale, WI · On-site
$21 - $24/hr
Pre-Entry level engineering position joining the team that develops Equipment Controls, Building ... Working on small projects that aid in the development, simulation and emulation of our products.
Control Applications Tech Intern II
Glendale, WI · On-site
$21 - $24/hr
Pre-Entry level engineering position joining the team that develops Equipment Controls, Building ... Working on small projects that aid in the development, simulation and emulation of our products.
Control Applications Tech Intern II
Glendale, WI · On-site
$21 - $24/hr
Pre-Entry level engineering position joining the team that develops Equipment Controls, Building ... Working on small projects that aid in the development, simulation and emulation of our products.
Contract Technical Recruiter
San Jose, CA · On-site
... a range of engineering and specialized domains. Key Responsibilities: * Manage full-cycle ... Competitive hourly rate based on experience We're doing work that matters. Help us solve what ...
Contract Technical Recruiter
San Jose, CA · On-site
... a range of engineering and specialized domains. Key Responsibilities: * Manage full-cycle ... Competitive hourly rate based on experience We're doing work that matters. Help us solve what ...
... a range of engineering and specialized domains. Key Responsibilities: * Manage full-cycle ... Competitive hourly rate based on experience We're doing work that matters. Help us solve what ...
... a range of engineering and specialized domains. Key Responsibilities: * Manage full-cycle ... Competitive hourly rate based on experience We're doing work that matters. Help us solve what ...
... a range of engineering and specialized domains. Key Responsibilities: * Manage full-cycle ... Competitive hourly rate based on experience We're doing work that matters. Help us solve what ...
... a range of engineering and specialized domains. Key Responsibilities: * Manage full-cycle ... Competitive hourly rate based on experience We're doing work that matters. Help us solve what ...
Cyber Network Ops (CNO) Advisor
Reston, VA · On-site
This role will be filled as a part-time hourly position. Additional vacancies may be filled from ... adversary emulation operations including passive and active reconnaissance, social engineering ...
Cyber Network Ops (CNO) Advisor
Reston, VA · On-site
This role will be filled as a part-time hourly position. Additional vacancies may be filled from ... adversary emulation operations including passive and active reconnaissance, social engineering ...
Security Software Engineer (L4), Detection Engineering
$260K - $459K/yr
DetEng is part of a larger Detection and Response team which includes Attacker Emulation, Security ... Full-time hourly employees accrue 35 days annually for paid time off to be used for vacation ...
Security Software Engineer (L4), Detection Engineering
$260K - $459K/yr
DetEng is part of a larger Detection and Response team which includes Attacker Emulation, Security ... Full-time hourly employees accrue 35 days annually for paid time off to be used for vacation ...
Security Software Engineer (L4), Detection Engineering
$260K - $459K/yr
DetEng is part of a larger Detection and Response team which includes Attacker Emulation, Security ... Full-time hourly employees accrue 35 days annually for paid time off to be used for vacation ...
Security Software Engineer (L4), Detection Engineering
$260K - $459K/yr
DetEng is part of a larger Detection and Response team which includes Attacker Emulation, Security ... Full-time hourly employees accrue 35 days annually for paid time off to be used for vacation ...
OR · On-site
$260K - $459K/yr
DetEng is part of a larger Detection and Response team which includes Attacker Emulation, Security ... Full-time hourly employees accrue 35 days annually for paid time off to be used for vacation ...
R&D Intern - Wireless Systems Engineer - 2026
Los Angeles, CA · On-site
$42/hr
Lab equipment for signal generation, channel emulation, spectrum analysis, etc. * Custom test ... CA Pay Range: $28.60 - $33.80 / hourly [in-progress Bachelor's degree] CA Pay Range: $42.00 ...
R&D Intern - Wireless Systems Engineer - 2026
Los Angeles, CA · On-site
$42/hr
Lab equipment for signal generation, channel emulation, spectrum analysis, etc. * Custom test ... CA Pay Range: $28.60 - $33.80 / hourly [in-progress Bachelor's degree] CA Pay Range: $42.00 ...
Lab equipment for signal generation, channel emulation, spectrum analysis, etc. * Custom test ... CA Pay Range: $28.60 - $33.80 / hourly [in-progress Bachelor's degree] CA Pay Range: $42.00 ...
Lab equipment for signal generation, channel emulation, spectrum analysis, etc. * Custom test ... CA Pay Range: $28.60 - $33.80 / hourly [in-progress Bachelor's degree] CA Pay Range: $42.00 ...
Lab equipment for signal generation, channel emulation, spectrum analysis, etc. * Custom test ... CA Pay Range: $28.60 - $33.80 / hourly [in-progress Bachelor's degree] CA Pay Range: $42.00 ...
Lab equipment for signal generation, channel emulation, spectrum analysis, etc. * Custom test ... CA Pay Range: $28.60 - $33.80 / hourly [in-progress Bachelor's degree] CA Pay Range: $42.00 ...
Engineering, Operations, Service Desk, Applications and BISOs on matters related to security ... Purple team experience conducting attacker simulation and adversary emulation * System ...
New
Engineering, Operations, Service Desk, Applications and BISOs on matters related to security ... Purple team experience conducting attacker simulation and adversary emulation * System ...
New
Vulnerability Researcher: Senior Levels (Applicants must alread with Security Clearance
$43.27 - $108.17/hr
Reverse engineering utilizing any of IDA, Ghidra, or Binary Ninja * Experience with dynamic and ... Performing full system emulation for research and analysis * Understanding of network protocols
Vulnerability Researcher: Senior Levels (Applicants must alread with Security Clearance
$43.27 - $108.17/hr
Reverse engineering utilizing any of IDA, Ghidra, or Binary Ninja * Experience with dynamic and ... Performing full system emulation for research and analysis * Understanding of network protocols
Vulnerability Researcher: Senior Levels (Applicants must already hold a TS clearance or higher) ...
$43.27 - $108.17/hr
Reverse engineering utilizing any of IDA, Ghidra, or Binary Ninja * Experience with dynamic and ... Performing full system emulation for research and analysis * Understanding of network protocols
Vulnerability Researcher: Senior Levels (Applicants must already hold a TS clearance or higher) ...
$43.27 - $108.17/hr
Reverse engineering utilizing any of IDA, Ghidra, or Binary Ninja * Experience with dynamic and ... Performing full system emulation for research and analysis * Understanding of network protocols
Hourly Emulation Engineer information
See salary details
$25.48 - $30.14
1% of jobs
$30.14 - $34.79
5% of jobs
$34.79 - $39.44
9% of jobs
$43.46 is the 25th percentile. Wages below this are outliers.
$39.44 - $44.10
12% of jobs
$44.10 - $48.75
10% of jobs
The median wage is $53.08 / hr.
$48.75 - $53.41
15% of jobs
$53.41 - $58.06
15% of jobs
$61.36 is the 75th percentile. Wages above this are outliers.
$58.06 - $62.72
13% of jobs
$62.72 - $67.37
10% of jobs
$67.37 - $72.03
10% of jobs
$72.03 - $76.68
2% of jobs
$25
$53
$76
How much do hourly emulation engineer jobs pay per hour?
Is there a shortage of hardware engineers?
What type of engineer is most in demand?
What is the difference between Hourly Emulation Engineer vs Hardware Test Engineer?
| Aspect | Hourly Emulation Engineer | Hardware Test Engineer |
|---|---|---|
| Required Credentials | Bachelor's in Electrical Engineering or related; experience with emulation tools | Bachelor's in Electrical Engineering or related; experience with hardware testing |
| Work Environment | Design labs, emulation platforms, simulation environments | Manufacturing floors, testing labs, hardware validation setups |
| Employer & Industry Usage | Semiconductor, electronics design companies, chip manufacturers | Electronics manufacturing, consumer electronics, hardware development |
| Common Search & Comparison | Yes, often compared for hardware validation roles | Yes, similar in hardware testing focus |
Hourly Emulation Engineers focus on developing and validating hardware designs using emulation tools, while Hardware Test Engineers primarily perform physical testing and validation of hardware products. Both roles require technical expertise in electronics, but differ in their methods and environments.
What engineers make $500,000?
What is the highest paid engineer job?

Job description
Team Description:
The Brain Interfaces Soc Department delivers chip architecture and silicon implementation of neural recording and stimulation system-on-chip (SoC) for high-bandwidth brain-computer interfaces. We have crafted a team of exceptional engineers whose mission is to push the frontiers of what is possible today and define the future.
Job Description and Responsibilities:
We are looking for experienced and hands-on engineers with a creative and initiative mindset, who are interested in exploring the next-generation chip design with advanced architectures and hardware accelerators with a goal of enhancing the energy efficiency, information entropy, and scalability of our wireless brain-computer interfaces towards the physical limit of silicon technology. The ideal candidates are energetic people who get excited about building things, are highly analytical, and enjoy tackling new problems. You will have the opportunity to collaborate closely with chip designers, electrical engineers, algorithms engineers, and software engineers on a small, agile team. As a Digital IC Design Engineer Intern, your responsibilities will include:
- Micro-architecture design and RTL implementation of:Â
- Low-power digital signal processors
- Low-power general-purpose hardware accelerators
- Low-power graphics processing units
- Low-power radio MAC/PHY
- Low-power serial link MAC/PHY
- Design and implementation of hardware/software interface with firmware engineers
- Application-specific architecture optimization including:
- Complex system modeling for energy and performance benchmarks
- Workload analysis and modeling
- Leveraging architecture-level design trade-offs with process technology and workload type
- Balancing energy efficiency and performance under manufacturing process variationÂ
- Complex system-on-chip verification
- Behavioral level modeling and model equivalence check
- FPGA emulation
- Analog mixed-signal co-simulation
- Design for testabilityÂ
- Collaboration on silicon bring-up tests with silicon validation engineersÂ
Required Qualifications:
- Evidence of exceptional ability in electrical engineering, computer science, or computer engineering
- 2+ years of experience in digital design
- Proficient in SystemVerilog, C/C++, Python
- Experience working on complex digital systems from architecture, microarchitecture, and RTL, using industry standard tools
- Experience in designing digital signal processing pipelines, from algorithm to RTL
Preferred Qualifications:
- Experience in architecture optimization with process technology customization
- Experience in the verification of complex digital systems, using industry standard tools
- Experience in the physical design of complex digital systems, using industry standard tools
- Experience testing and debugging digital system-on-a-chips
- Functional modeling experience and logic verification with SystemVerilog, SystemC/C++, or UVMÂ
- Experience automating tool flows
- Experience with embedded design
- Experience in processor instruction set architecture design
- Experience in compiler back-end design and customization
- Experience designing PCBs or writing firmware.
Expected Compensation:
The anticipated hourly rate for this position is listed below.
California Hourly Flat Rate:
$35/Hr USD
About NEURALINK
Sourced by ZipRecruiter
Industry
Biotechnology research and development
Company size
201 - 500 Employees
Headquarters location
San Francisco, CA, US
Year founded
2016