... ASIC RTL design and verification, hardware design, and signal integrity, among others, to deliver ... Drive and close new business opportunities selling Fidus design services and engineering products.
... ASIC RTL design and verification, hardware design, and signal integrity, among others, to deliver ... Drive and close new business opportunities selling Fidus design services and engineering products.
Design Verification Engineer (Silicon Engineering)
Redmond, WA · On-site
$145K - $195K/yr
Responsible for digital ASIC verification at block and system level * Write and review test plans ... RTL design, chip bring-up, and post-silicon validation experience * Ability to work in a dynamic ...
Design Verification Engineer (Silicon Engineering)
Redmond, WA · On-site
$145K - $195K/yr
Responsible for digital ASIC verification at block and system level * Write and review test plans ... RTL design, chip bring-up, and post-silicon validation experience * Ability to work in a dynamic ...
Design Verification Engineer (Silicon Engineering)
Redmond, WA · On-site
$125 - $145/hr
Responsible for digital ASIC verification at block and system level * Write and review test plans ... RTL design, chip bring‑up, and post‑silicon validation experience * Ability to work in a ...
Design Verification Engineer (Silicon Engineering)
Redmond, WA · On-site
$125 - $145/hr
Responsible for digital ASIC verification at block and system level * Write and review test plans ... RTL design, chip bring‑up, and post‑silicon validation experience * Ability to work in a ...
Senior Design Engineer : Custom Digital Hard Macros (Physical IP)
Seattle, WA · On-site
$120 - $190/hr
As a Design Engineer, you will contribute to the implementation and delivery of digital hard macros ... You will work across RTL, physical implementation, timing closure, simulation, characterization ...
Senior Design Engineer : Custom Digital Hard Macros (Physical IP)
Seattle, WA · On-site
$120 - $190/hr
As a Design Engineer, you will contribute to the implementation and delivery of digital hard macros ... You will work across RTL, physical implementation, timing closure, simulation, characterization ...
Senior ASIC Design Engineer - Terawave
Seattle, WA · On-site
$230K - $322K/yr
Austin, TX; Kent, WA. Key Responsibilities: Design and Verification * Verilog ... ASIC to/from FPGA flow Minimum Qualifications: * BS, MS in Electrical Engineering or a related ...
Senior ASIC Design Engineer - Terawave
Seattle, WA · On-site
$230K - $322K/yr
Austin, TX; Kent, WA. Key Responsibilities: Design and Verification * Verilog ... ASIC to/from FPGA flow Minimum Qualifications: * BS, MS in Electrical Engineering or a related ...
FPGA Engineer, Amazon LEO OISL
Redmond, WA · On-site
$145K - $187K/yr
... design engineer will work with systems teams to define/develop/implement/test/release FPGA based ... RTL Design-Physical Implementation-Timing Closure-Simulation Validation- Lab Based Silicon ...
FPGA Engineer, Amazon LEO OISL
Redmond, WA · On-site
$145K - $187K/yr
... design engineer will work with systems teams to define/develop/implement/test/release FPGA based ... RTL Design-Physical Implementation-Timing Closure-Simulation Validation- Lab Based Silicon ...
Senior FPGA Engineer, LEO Payload FPGA, Amazon Leo Hardware Development
Redmond, WA · On-site
$145K - $187K/yr
The FPGA design engineer will work with systems teams to define/develop/implement/test/release FPGA ... RTL Design-Physical Implementation-Timing Closure-Simulation Validation- Lab Based Silicon ...
Senior FPGA Engineer, LEO Payload FPGA, Amazon Leo Hardware Development
Redmond, WA · On-site
$145K - $187K/yr
The FPGA design engineer will work with systems teams to define/develop/implement/test/release FPGA ... RTL Design-Physical Implementation-Timing Closure-Simulation Validation- Lab Based Silicon ...
Senior FPGA Engineer, Payload Hardware Development, Leo PAA Hardware
Redmond, WA · On-site
$145K - $187K/yr
The FPGA design engineer will work with systems teams to define/develop/implement/test/release FPGA ... RTL Design-Physical Implementation-Timing Closure-Simulation Validation- Lab Based Silicon ...
Senior FPGA Engineer, Payload Hardware Development, Leo PAA Hardware
Redmond, WA · On-site
$145K - $187K/yr
The FPGA design engineer will work with systems teams to define/develop/implement/test/release FPGA ... RTL Design-Physical Implementation-Timing Closure-Simulation Validation- Lab Based Silicon ...
FPGA Engineer, Amazon LEO OISL
$145K - $187K/yr
... design engineer will work with systems teams to define/develop/implement/test/release FPGA based ... RTL Design-Physical Implementation-Timing Closure-Simulation Validation- Lab Based Silicon ...
FPGA Engineer, Amazon LEO OISL
$145K - $187K/yr
... design engineer will work with systems teams to define/develop/implement/test/release FPGA based ... RTL Design-Physical Implementation-Timing Closure-Simulation Validation- Lab Based Silicon ...
FPGA Engineer, Amazon LEO OISL
Redmond, WA · On-site
$145K - $187K/yr
... design engineer will work with systems teams to define/develop/implement/test/release FPGA based ... RTL Design-Physical Implementation-Timing Closure-Simulation Validation- Lab Based Silicon ...
FPGA Engineer, Amazon LEO OISL
Redmond, WA · On-site
$145K - $187K/yr
... design engineer will work with systems teams to define/develop/implement/test/release FPGA based ... RTL Design-Physical Implementation-Timing Closure-Simulation Validation- Lab Based Silicon ...
FPGA Engineer, Amazon LEO OISL
Redmond, WA · On-site
$145K - $187K/yr
... design engineer will work with systems teams to define/develop/implement/test/release FPGA based ... RTL Design-Physical Implementation-Timing Closure-Simulation Validation- Lab Based Silicon ...
FPGA Engineer, Amazon LEO OISL
Redmond, WA · On-site
$145K - $187K/yr
... design engineer will work with systems teams to define/develop/implement/test/release FPGA based ... RTL Design-Physical Implementation-Timing Closure-Simulation Validation- Lab Based Silicon ...
Senior FPGA Engineer, Payload Hardware Development, Leo PAA Hardware
Redmond, WA · On-site
$145K - $187K/yr
... design engineer will work with systems teams to define/develop/implement/test/release FPGA based ... RTL Design-Physical Implementation-Timing Closure-Simulation Validation- Lab Based Silicon ...
Senior FPGA Engineer, Payload Hardware Development, Leo PAA Hardware
Redmond, WA · On-site
$145K - $187K/yr
... design engineer will work with systems teams to define/develop/implement/test/release FPGA based ... RTL Design-Physical Implementation-Timing Closure-Simulation Validation- Lab Based Silicon ...
Senior FPGA Engineer, Payload Hardware Development, Leo PAA Hardware
Redmond, WA · On-site
$145K - $187K/yr
... design engineer will work with systems teams to define/develop/implement/test/release FPGA based ... RTL Design-Physical Implementation-Timing Closure-Simulation Validation- Lab Based Silicon ...
Senior FPGA Engineer, Payload Hardware Development, Leo PAA Hardware
Redmond, WA · On-site
$145K - $187K/yr
... design engineer will work with systems teams to define/develop/implement/test/release FPGA based ... RTL Design-Physical Implementation-Timing Closure-Simulation Validation- Lab Based Silicon ...
Senior FPGA Engineer, LEO Payload FPGA, Amazon Leo Hardware Development
Redmond, WA · On-site
$145K - $187K/yr
... design engineer will work with systems teams to define/develop/implement/test/release FPGA based ... RTL Design-Physical Implementation-Timing Closure-Simulation Validation- Lab Based Silicon ...
Senior FPGA Engineer, LEO Payload FPGA, Amazon Leo Hardware Development
Redmond, WA · On-site
$145K - $187K/yr
... design engineer will work with systems teams to define/develop/implement/test/release FPGA based ... RTL Design-Physical Implementation-Timing Closure-Simulation Validation- Lab Based Silicon ...
Senior FPGA Engineer, LEO Payload FPGA, Amazon Leo Hardware Development
Redmond, WA · On-site
$145K - $187K/yr
... design engineer will work with systems teams to define/develop/implement/test/release FPGA based ... RTL Design-Physical Implementation-Timing Closure-Simulation Validation- Lab Based Silicon ...
Senior FPGA Engineer, LEO Payload FPGA, Amazon Leo Hardware Development
Redmond, WA · On-site
$145K - $187K/yr
... design engineer will work with systems teams to define/develop/implement/test/release FPGA based ... RTL Design-Physical Implementation-Timing Closure-Simulation Validation- Lab Based Silicon ...
Principal Design Verification Engineer (Silicon Engineering)
Redmond, WA · On-site
$210K - $335K/yr
Responsible for digital ASIC and/or FPGA verification at block and system level * Lead and execute ... RTL design, chip bring-up, and post-silicon validation experience * Ability to work in a dynamic ...
Principal Design Verification Engineer (Silicon Engineering)
Redmond, WA · On-site
$210K - $335K/yr
Responsible for digital ASIC and/or FPGA verification at block and system level * Lead and execute ... RTL design, chip bring-up, and post-silicon validation experience * Ability to work in a dynamic ...
Senior Silicon Physical Design Engineer - TeraWave
$230K - $322K/yr
Execute RTL-to-GDS physical implementation of SoCs for space applications: synthesis, floor ... Understanding of thermal considerations in ASIC design * Familiarity with space qualification ...
Senior Silicon Physical Design Engineer - TeraWave
$230K - $322K/yr
Execute RTL-to-GDS physical implementation of SoCs for space applications: synthesis, floor ... Understanding of thermal considerations in ASIC design * Familiarity with space qualification ...
Senior ASIC Verification Engineer, Space & Satellite
Redmond, WA · On-site
$165 - $230/hr
United States Digital Space LLC in Redmond is seeking a Sr. ASIC Design Verification Engineer to develop cutting-edge ASICs enabling connectivity in remote areas. You will be part of a team building ...
Senior ASIC Verification Engineer, Space & Satellite
Redmond, WA · On-site
$165 - $230/hr
United States Digital Space LLC in Redmond is seeking a Sr. ASIC Design Verification Engineer to develop cutting-edge ASICs enabling connectivity in remote areas. You will be part of a team building ...
Senior FPGA Engineer
$215K - $250K/yr
Kapta Space is seeking a Senior FPGA Engineer to lead RTL design and FPGA development for radar operation and algorithm implementation. Kapta Space is seeking FPGA Engineers with experience in ...
Quick apply
Senior FPGA Engineer
$215K - $250K/yr
Kapta Space is seeking a Senior FPGA Engineer to lead RTL design and FPGA development for radar operation and algorithm implementation. Kapta Space is seeking FPGA Engineers with experience in ...
FPGA Designer
Seattle, WA · On-site
$120 - $180/hr
RTL design and verification including test benches, functional simulations, and timing closure ... Embraces AI as part of a modern engineering toolkit * Degree as a B.A.Sc., B.Eng. or equivalent
New
FPGA Designer
Seattle, WA · On-site
$120 - $180/hr
RTL design and verification including test benches, functional simulations, and timing closure ... Embraces AI as part of a modern engineering toolkit * Degree as a B.A.Sc., B.Eng. or equivalent
New
Freelance Asic Rtl Design Engineer information
See Seattle, WA salary details
$26.77 is the 25th percentile. Wages below this are outliers.
$16.96 - $29.10
31% of jobs
The median wage is $36.58 / hr.
$29.10 - $41.23
31% of jobs
$41.23 - $53.37
4% of jobs
$63.99 is the 75th percentile. Wages above this are outliers.
$53.37 - $65.51
10% of jobs
$65.51 - $77.64
9% of jobs
$77.64 - $89.78
5% of jobs
$89.78 - $101.92
0% of jobs
$101.92 - $114.05
8% of jobs
$114.05 - $126.19
0% of jobs
$126.19 - $138.32
0% of jobs
$138.32 - $150.46
1% of jobs
$16
$54
$150
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Full-time
Re-posted 19 days ago
Job description
With over 20 years of experience and 4,000+ projects completed, our precision-driven process ensures that designs and prototypes reach the market faster, earning us a reputation for transparency and a commitment to getting it right the first time. Our diverse clientele includes industries such as Telecom/Datacom, Aerospace and Defence, Consumer, Semiconductors, Industrial/Automotive Controls, and Medical.
The role
We are seeking a technically fluent, commercially driven hunter with deep familiarity with hardware design cycles, a track record opening net-new logos, and proven success selling high-complexity North American engineering services into semiconductor, Telecom/Datacom, or Aerospace & Defence markets. The preferred candidate will be located within a key target territory - Pacific Northwest (WA/OR), North Central (Chicago or Saint Paul), South East (Atlanta) or US Central South (TX) - and required to travel 50% of the time within territory.
What's in it for you
- Working with a Tier 1 high-tech design house in a rapidly expanding industry: We work on advanced technologies enabling AI, IoT, Autonomous Vehicles, and Fintech.
- Join an evolving company: Make your voice heard and create the change you want to see.
- Work with Cutting Edge Technology: You will have the opportunity to work on a variety of leading technologies and be part of a team that solves the hard problems that new technologies present.
- Generous Benefits Package and Company Culture: Our employees are everything to us. Featuring a full benefits package, healthy work/life balance, and a company culture where you feel like you are part of a family.
- Join a Company Built for Growth: We are actively pursuing large-scale growth, both organically and through strategic acquisitions, to expand our market leadership.
A look into the role
- Drive and close new business opportunities selling Fidus design services and engineering products.
- Generate revenue through prospecting, up-selling, and cross-selling activities within a defined territory or account.
- Leverage existing partner relationships in the industry for introductions to new contacts.
- Develop in-depth knowledge of clients' business priorities, design challenges, and roadmap initiatives that can be translated into opportunities for Fidus to win their engineering business.
- Position Fidus as an early-stage design consultant in the conception and delivery of customers' innovative hardware products.
- Confidently position and defend premium North American engineering rates by articulating design risk reduction, first-pass silicon success, and co-location advantages - without reliance on offshore cost arbitrage.
- Build and leverage relationships within the AMD, Altera, Intel, and Xilinx field application engineering (FAE) and silicon distribution ecosystems to generate pipeline and qualified referrals.
Requirements
Attributes and qualifications required
- Minimum 8 years of sales experience working with semiconductors, electronic design services, FPGA ecosystems, embedded software, or adjacent engineering services industries.
- Completion of a Bachelor's degree or the equivalent.
- Prior experience selling services in both turnkey design and onshore outsourced staffing, for high-speed, high-complexity designs.
- Experience selling within or alongside the semiconductor silicon ecosystem - including FPGA/ASIC silicon vendors or their value-added distribution partners - is a strong asset.
- Bachelor's degree in Engineering or Business will be considered a strong asset.
- Ability to successfully demonstrate the required technical competency in electronic design services or similar industries.
- Familiarity with ITAR, Controlled Goods programmes, or selling into defence/aerospace prime contractors is a meaningful asset for candidates targeting our Aerospace & Defence and secure industrial verticals.
- Embraces AI as part of day-to-day operations to improve efficiency and output quality.
- Ability to travel up to 50%.
If all of this excites you, has your attention, and you can't wait to join our amazing team and work environment, then we want to hear from you!
Curious what it's actually like to work here? Take a look at our Working at Fidus page.
Thank you for your interest in Fidus. We welcome and encourage diverse candidates to apply. Accommodations are available upon request for candidates taking part in all aspects of the selection process. Fidus is committed to creating a diverse environment and is proud to be an equal opportunity employer.