Asic Design Engineer Location: Mountain View CA (Remote) Note: Seeking candidate with Fusion ... Good in understanding RTL Design and Digital concepts * Strong experience with EDA tools: Fusion ...
Asic Design Engineer Location: Mountain View CA (Remote) Note: Seeking candidate with Fusion ... Good in understanding RTL Design and Digital concepts * Strong experience with EDA tools: Fusion ...
Staff RTL Design Engineer
Austin, TX · On-site
$198K - $268K/yr
As an Interconnect RTL Design Engineer, you will be part of the Systems team focused on next-generation interconnects targeting high-end mobile, automotive, networking, and enterprise markets! You ...
Staff RTL Design Engineer
Austin, TX · On-site
$198K - $268K/yr
As an Interconnect RTL Design Engineer, you will be part of the Systems team focused on next-generation interconnects targeting high-end mobile, automotive, networking, and enterprise markets! You ...
Staff RTL Design Engineer
Austin, TX · Hybrid
$198K - $268K/yr
As an Interconnect RTL Design Engineer, you will be part of the Systems team focused on next-generation interconnects targeting high-end mobile, automotive, networking, and enterprise markets! You ...
Staff RTL Design Engineer
Austin, TX · Hybrid
$198K - $268K/yr
As an Interconnect RTL Design Engineer, you will be part of the Systems team focused on next-generation interconnects targeting high-end mobile, automotive, networking, and enterprise markets! You ...
... SR. RTL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in ... ASIC/SoC system integration experience * Experience with embedded CPU subsystems * Experience with ...
... SR. RTL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in ... ASIC/SoC system integration experience * Experience with embedded CPU subsystems * Experience with ...
RTL Design Engineer
Austin, TX · On-site
$105K - $200K/yr
Medical
Retirement
PTO
... Engineering • At least 1+ years of coursework or experience in the following areas: oBasic Logic Design oMicroprocessors oComputer Architecture oDigital design and RTL coding oVerilog/SystemVerilog ...
RTL Design Engineer
Austin, TX · On-site
$105K - $200K/yr
Medical
Retirement
PTO
... Engineering • At least 1+ years of coursework or experience in the following areas: oBasic Logic Design oMicroprocessors oComputer Architecture oDigital design and RTL coding oVerilog/SystemVerilog ...
As a CPU Core RTL Design Engineer, you will help design and optimize next-generation high ... Experience with Verilog/SystemVerilog RTL development in CPU, SoC, or ASIC environments * Strong ...
As a CPU Core RTL Design Engineer, you will help design and optimize next-generation high ... Experience with Verilog/SystemVerilog RTL development in CPU, SoC, or ASIC environments * Strong ...
Senior ASIC Design Engineer
$140K - $175K/yr
Perform hands-on ASIC design including microarchitecture, RTL development, testing, and integration. * Work closely with Atom Computing's quantum physicists, optical engineers, hardware and software ...
New
Quick apply
Senior ASIC Design Engineer
$140K - $175K/yr
Perform hands-on ASIC design including microarchitecture, RTL development, testing, and integration. * Work closely with Atom Computing's quantum physicists, optical engineers, hardware and software ...
New
Join the NVIDIA System-On-Chip (SOC) group as an ASIC Design Engineer and make a broad impact. You ... Run and debug RTL checks to ensure design quality (e.g., cross clock domains (CDC), clocks, reset ...
Join the NVIDIA System-On-Chip (SOC) group as an ASIC Design Engineer and make a broad impact. You ... Run and debug RTL checks to ensure design quality (e.g., cross clock domains (CDC), clocks, reset ...
SR. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our ... RTL/design tradeoffs * Resolve design/timing/congestion and flow issues, identify potential ...
SR. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our ... RTL/design tradeoffs * Resolve design/timing/congestion and flow issues, identify potential ...
RTL Design Engineer
Austin, TX · On-site
$105K - $200K/yr
Medical
Retirement
PTO
Develops the logic design, register transfer level (RTL) coding, and simulation for a CPU required ... Electrical or Computer Engineering or any STEM related education with at least 2+ years of ...
RTL Design Engineer
Austin, TX · On-site
$105K - $200K/yr
Medical
Retirement
PTO
Develops the logic design, register transfer level (RTL) coding, and simulation for a CPU required ... Electrical or Computer Engineering or any STEM related education with at least 2+ years of ...
Join the NVIDIA System-On-Chip (SOC) group as an ASIC Design Engineer and make a broad impact. You ... Run and debug RTL checks to ensure design quality (e.g., cross clock domains (CDC), clocks, reset ...
Join the NVIDIA System-On-Chip (SOC) group as an ASIC Design Engineer and make a broad impact. You ... Run and debug RTL checks to ensure design quality (e.g., cross clock domains (CDC), clocks, reset ...
ASIC Implementation Engineer - Static Verification Responsibilities: * Perform Flat and ... Experience with RTL design using SystemVerilog or other HDL * Experience with communicating across ...
ASIC Implementation Engineer - Static Verification Responsibilities: * Perform Flat and ... Experience with RTL design using SystemVerilog or other HDL * Experience with communicating across ...
ASIC Engineer, Power
Austin, TX · On-site +1
$146K/yr
As an ASIC Engineer specializing in power on the EDA Infrastructure team, you will develop and ... Collaborate with RTL design, physical design, and verification teams to identify and resolve power ...
ASIC Engineer, Power
Austin, TX · On-site +1
$146K/yr
As an ASIC Engineer specializing in power on the EDA Infrastructure team, you will develop and ... Collaborate with RTL design, physical design, and verification teams to identify and resolve power ...
CPU RTL Design Engineer
Austin, TX · On-site
$141K - $269K/yr
Medical
Retirement
PTO
As a CPU Logic Design Engineer, you will play a critical role in designing and optimizing the logic for Intel's cutting-edge processors. You will drive the development of register transfer level (RTL ...
CPU RTL Design Engineer
Austin, TX · On-site
$141K - $269K/yr
Medical
Retirement
PTO
As a CPU Logic Design Engineer, you will play a critical role in designing and optimizing the logic for Intel's cutting-edge processors. You will drive the development of register transfer level (RTL ...
NVIDIA is seeking ASIC Design Engineers with experience in agentic AI to help design and implement ... Experience in micro-architecture and RTL development (Verilog) in complex designs. * Deep ...
NVIDIA is seeking ASIC Design Engineers with experience in agentic AI to help design and implement ... Experience in micro-architecture and RTL development (Verilog) in complex designs. * Deep ...
CPU RTL Design Engineer
Austin, TX · On-site
$141K - $269K/yr
Medical
Retirement
PTO
As a CPU Logic Design Engineer, you will play a critical role in designing and optimizing the logic for Intel's cutting-edge processors. You will drive the development of register transfer level (RTL ...
CPU RTL Design Engineer
Austin, TX · On-site
$141K - $269K/yr
Medical
Retirement
PTO
As a CPU Logic Design Engineer, you will play a critical role in designing and optimizing the logic for Intel's cutting-edge processors. You will drive the development of register transfer level (RTL ...
ASIC Engineer, Physical Design Responsibilities: * Lead physical implementation of complex ASIC ... Collaborate with RTL design and architecture teams to provide physical design feedback on ...
ASIC Engineer, Physical Design Responsibilities: * Lead physical implementation of complex ASIC ... Collaborate with RTL design and architecture teams to provide physical design feedback on ...
... SR. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our ... RTL/design tradeoffs * Resolve design/timing/congestion and flow issues, identify potential ...
... SR. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our ... RTL/design tradeoffs * Resolve design/timing/congestion and flow issues, identify potential ...
Interconnect Micro-architect/RTL Design Engineer
Austin, TX · On-site
$156K/yr
You are an experienced RTL design engineer with a passion for complex processor systems and interconnect architecture. You bring deep technical expertise, a structured problem-solving approach, and ...
Interconnect Micro-architect/RTL Design Engineer
Austin, TX · On-site
$156K/yr
You are an experienced RTL design engineer with a passion for complex processor systems and interconnect architecture. You bring deep technical expertise, a structured problem-solving approach, and ...
Join the NVIDIA System-On-Chip (SOC) group as an ASIC Design Engineer and make a broad impact. You ... Learn and run RTL checks to ensure design quality (e.g., cross clock domains (CDC), clocks, reset ...
Join the NVIDIA System-On-Chip (SOC) group as an ASIC Design Engineer and make a broad impact. You ... Learn and run RTL checks to ensure design quality (e.g., cross clock domains (CDC), clocks, reset ...
Freelance Asic Rtl Design Engineer information
See Austin, TX salary details
$23.32 is the 25th percentile. Wages below this are outliers.
$14.77 - $25.34
31% of jobs
The median wage is $31.86 / hr.
$25.34 - $35.91
31% of jobs
$35.91 - $46.48
4% of jobs
$55.73 is the 75th percentile. Wages above this are outliers.
$46.48 - $57.05
10% of jobs
$57.05 - $67.63
9% of jobs
$67.63 - $78.20
5% of jobs
$78.20 - $88.77
0% of jobs
$88.77 - $99.34
8% of jobs
$99.34 - $109.91
0% of jobs
$109.91 - $120.48
0% of jobs
$120.48 - $131.05
1% of jobs
$14
$47
$131
How much do freelance asic rtl design engineer jobs pay per hour?
As of Aug 12, 2026, the average hourly pay for freelance asic rtl design engineer in Austin, TX is $47.29, according to ZipRecruiter salary data. Most workers in this role earn between $24.09 and $61.25 per hour, depending on experience, location, and employer.
How much does a Freelance ASIC RTL Design Engineer make?
Freelance ASIC RTL Design Engineers typically earn between $50 and $150 per hour, depending on experience, project complexity, and location. Rates can vary based on expertise in hardware description languages like Verilog or VHDL and familiarity with FPGA or ASIC design tools.
Are freelance ASIC RTL design engineers in demand?
Freelance ASIC RTL design engineers are in demand due to the growing need for custom chip development in industries like telecommunications, AI, and consumer electronics. Skills in hardware description languages such as Verilog or VHDL, along with experience in FPGA prototyping, enhance employability in this competitive field.
What are the most commonly searched types of Asic Rtl Design Engineer jobs in Austin, TX? The most popular types of Asic Rtl Design Engineer jobs in Austin, TX are:
What are popular job titles related to Freelance Asic Rtl Design Engineer jobs in Austin, TX? For Freelance Asic Rtl Design Engineer jobs in Austin, TX, the most frequently searched job titles are:
What job categories do people searching Freelance Asic Rtl Design Engineer jobs in Austin, TX look for? The top searched job categories for Freelance Asic Rtl Design Engineer jobs in Austin, TX are:
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Full-time
Re-posted 4 days ago
Arrow Electronics rating
7.7
Based on 19 frontline employees who took The Breakroom Quiz
Job description
Position:ASIC Design Engineer (eInfochips)
Job Description:
Location:US-CA-Mountain View, California (Google)
Time Type:Full time
Job Category:Engineering ServicesEEO Statement:
Job Description:
Role: Asic Design Engineer
Location: Mountain View CA (Remote)
Note: Seeking candidate with Fusion Compiler and Scripting experince.
What candidate will Be Doing:
- Proficient in Verilog/System Verilog coding constructs.
- Knowledge of front-end tools (Verilog simulators, Connectivity tools, CDC checkers, low power static checkers, linting)
- Experience with high speed PCIe designs and protocols.
- Experience with Industry standard interface protocols such as AXI, APB, etc.
- Experience with ARM Fabric IPs.
- Experience with IPXACT.
- Understanding of Computer Architecture fundamentals.
- Ability to write scripts using Python, Tcl, Perl etc.
- Experience in EDA tools such as VCS, VCLP, Spyglass Lint, Questa CDC, Fusion Compiler, Design Compiler, Genus.
- Proficiency with UPF (Low power intent)
- Proficiency in clock crossing techniques.
- Knowledge of Static Timing Analysis and understanding of timing signoff fundamentals.
What we are looking for:
- Good in understanding RTL Design and Digital concepts
- Strong experience with EDA tools: Fusion Compiler, CDC
- Scripting: Pearl, Python, TCL
- At-least 5+ years of experience in Verilog Design
- AMBA AXI bus along-with ARM or C based processor
- Ensure customer satisfaction.
- Reporting to customers on daily or weekly progress effectively
Work Arrangement Fully Onsite: Must be able to travel to an Arrow Client office location as requested by Arrow Client leadership.
Location: Mountain View CA (Remote)
About eInfochips:
eInfochips, an Arrow company (Fortune#154), is a leading global provider of product engineering and semiconductor design services. A rich history of over two decades, with over 500+ products developed and 40M deployments in 140 countries, eInfochips continues to fuel technological innovations in multiple verticals. eInfochips has strategic technology partnerships with Qualcomm, NVIDIA, NXP, Analog Devices, Texas Instruments, Amazon, Microsoft and Google to name a few. Along with Arrow’s $38B in revenues, 22,000 employees, and 345 locations serving over 80 countries, eInfochips is primed to accelerate connected products innovation for 150,000+ global clients. eInfochips acts as a catalyst to Arrow’s Sensor-to-Sunset initiative and offers complete edge-to-cloud capabilities for its clients. Please visit www.einfochips.com for our portfolio of product engineering services across
various industries & verticals.
Arrow’s Sensor-to-Sunset initiative and offers complete edge-to-cloud capabilities for its clients. Please visit www.einfochips.com for our portfolio of product engineering services across various industries C verticals.
EEO Statement:
Arrow is an equal opportunity employer. All applicants will be considered for employment without attention to race, color, religion, gender, age, sexual orientation, gender identity, national origin, veteran or disability status.
Location:US-CA-Mountain View, California (Google)
Time Type:Full time
Job Category:Engineering ServicesEEO Statement:
Arrow is an equal opportunity employer. All applicants will be considered for employment without attention to race, color, religion, gender, age, sexual orientation, gender identity, national origin, veteran or disability status. (Arrow EEO/AAP policy)
All Arrow job postings are for existing job vacancies. We anticipate this requisition will be open for a minimum of five days, though it may be open for a longer period of time. We encourage your prompt application.
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