Senior RTL Design Engineer
Austin, TX · On-site
S. in Electrical Engineering, Computer Engineering, or Computer Science * 5+ years of experience in ASIC RTL design * Solid foundation in computer architecture and digital logic design * Strong ...
Senior RTL Design Engineer
Austin, TX · On-site
S. in Electrical Engineering, Computer Engineering, or Computer Science * 5+ years of experience in ASIC RTL design * Solid foundation in computer architecture and digital logic design * Strong ...
Senior RTL Design Engineer
Austin, TX · On-site
$120K - $200K/yr
S. in Electrical Engineering, Computer Engineering, or Computer Science * 5+ years of experience in ASIC RTL design * Solid foundation in computer architecture and digital logic design * Strong ...
Senior RTL Design Engineer
Austin, TX · On-site
$120K - $200K/yr
S. in Electrical Engineering, Computer Engineering, or Computer Science * 5+ years of experience in ASIC RTL design * Solid foundation in computer architecture and digital logic design * Strong ...
Principal RTL Design Engineer
Austin, TX · On-site
B.S. in Electrical Engineering, Computer Engineering, or Computer Science * 7+ years of industry experience in ASIC RTL design * Mastery of synthesizable SystemVerilog for high-speed, high ...
Principal RTL Design Engineer
Austin, TX · On-site
B.S. in Electrical Engineering, Computer Engineering, or Computer Science * 7+ years of industry experience in ASIC RTL design * Mastery of synthesizable SystemVerilog for high-speed, high ...
Principal RTL Design Engineer
Austin, TX · On-site
$180K - $255K/yr
B.S. in Electrical Engineering, Computer Engineering, or Computer Science * 7+ years of industry experience in ASIC RTL design * Mastery of synthesizable SystemVerilog for high-speed, high ...
Principal RTL Design Engineer
Austin, TX · On-site
$180K - $255K/yr
B.S. in Electrical Engineering, Computer Engineering, or Computer Science * 7+ years of industry experience in ASIC RTL design * Mastery of synthesizable SystemVerilog for high-speed, high ...
Senior Manager, ASIC Design Engineering
Austin, TX · On-site +1
Cornelis Networks islooking for aSenior ASIC Design Engineering Managerto lead and grow our RTL design engineering team.Reporting to the VP of ASIC Engineering,with direct exposure toexecutive ...
Senior Manager, ASIC Design Engineering
Austin, TX · On-site +1
Cornelis Networks islooking for aSenior ASIC Design Engineering Managerto lead and grow our RTL design engineering team.Reporting to the VP of ASIC Engineering,with direct exposure toexecutive ...
ASIC Digital Design, Architect - 18388
Austin, TX · On-site
$181K/yr
Defining and developing ASIC RTL design and verification at both chip and block levels. * Creating ... Mentoring engineers and promoting best practices, technical excellence, and continuous improvement.
ASIC Digital Design, Architect - 18388
Austin, TX · On-site
$181K/yr
Defining and developing ASIC RTL design and verification at both chip and block levels. * Creating ... Mentoring engineers and promoting best practices, technical excellence, and continuous improvement.
RTL Design Engineer
Austin, TX · On-site
$120K - $225K/yr
We're hiring experienced RTL Design Engineers from junior to senior levels to play a key role in designing and implementing the components that will bring our next-generation AI processors to life.
RTL Design Engineer
Austin, TX · On-site
$120K - $225K/yr
We're hiring experienced RTL Design Engineers from junior to senior levels to play a key role in designing and implementing the components that will bring our next-generation AI processors to life.
RTL Design Engineer
Austin, TX · On-site
$120K - $225K/yr
We're hiring experienced RTL Design Engineers from junior to senior levels to play a key role in designing and implementing the components that will bring our next-generation AI processors to life.
Quick apply
RTL Design Engineer
Austin, TX · On-site
$120K - $225K/yr
We're hiring experienced RTL Design Engineers from junior to senior levels to play a key role in designing and implementing the components that will bring our next-generation AI processors to life.
RTL Design Engineer
Austin, TX · On-site
$120K - $225K/yr
We're hiring experienced RTL Design Engineers from junior to senior levels to play a key role in designing and implementing the components that will bring our next-generation AI processors to life.
RTL Design Engineer
Austin, TX · On-site
$120K - $225K/yr
We're hiring experienced RTL Design Engineers from junior to senior levels to play a key role in designing and implementing the components that will bring our next-generation AI processors to life.
ASIC Design Engineer - Hardware
Austin, TX · On-site
$125 - $150/hr
## ASIC Design Engineer - HardwareApplylocations: US, TX, Austintime type: Full timeposted on: Posted ... Run and debug RTL checks to ensure design quality (e.g., cross clock domains (CDC), clocks, reset ...
ASIC Design Engineer - Hardware
Austin, TX · On-site
$125 - $150/hr
## ASIC Design Engineer - HardwareApplylocations: US, TX, Austintime type: Full timeposted on: Posted ... Run and debug RTL checks to ensure design quality (e.g., cross clock domains (CDC), clocks, reset ...
SR. RTL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building ... ASIC/SoC system integration experience * Experience with embedded CPU subsystems * Experience with ...
SR. RTL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building ... ASIC/SoC system integration experience * Experience with embedded CPU subsystems * Experience with ...
RTL Design Engineer
$134K/yr
If you're passionate about taking on unsolved challenges, we have a great opportunity for a results-oriented and highly motivated RTL Design Engineer. This is an exciting position in the world class ...
RTL Design Engineer
$134K/yr
If you're passionate about taking on unsolved challenges, we have a great opportunity for a results-oriented and highly motivated RTL Design Engineer. This is an exciting position in the world class ...
Role and Responsibilities As an Engineer or Senior or Staff GPU RTL Design Engineer, you will ... Experience with front-end ASIC design flows, including linting, synthesis, timing analysis, and ...
Role and Responsibilities As an Engineer or Senior or Staff GPU RTL Design Engineer, you will ... Experience with front-end ASIC design flows, including linting, synthesis, timing analysis, and ...
RTL Design Engineer
$134K/yr
If you're passionate about taking on unsolved challenges, we have a great opportunity for a results-oriented and highly motivated RTL Design Engineer. This is an exciting position in the world class ...
RTL Design Engineer
$134K/yr
If you're passionate about taking on unsolved challenges, we have a great opportunity for a results-oriented and highly motivated RTL Design Engineer. This is an exciting position in the world class ...
Own full lifecycle recruiting for hardware roles across Design Verification, ASIC/RTL design, physical design, and PCB/systems engineering * Keep feedback loops tight across interviewers and ...
Own full lifecycle recruiting for hardware roles across Design Verification, ASIC/RTL design, physical design, and PCB/systems engineering * Keep feedback loops tight across interviewers and ...
ASIC Design Engineer
Austin, TX · On-site
$225K - $350K/yr
Role Overview As a Senior ASIC Design Engineer, you will take a leadership role in defining ... You will own the microarchitecture from high-level concept through RTL signoff, collaborating ...
ASIC Design Engineer
Austin, TX · On-site
$225K - $350K/yr
Role Overview As a Senior ASIC Design Engineer, you will take a leadership role in defining ... You will own the microarchitecture from high-level concept through RTL signoff, collaborating ...
ASIC Design Engineer
Austin, TX · On-site
$250/hr
As a Senior ASIC Design Engineer, you will take a leadership role in defining, implementing, and ... You will own the microarchitecture from high-level concept through RTL signoff, collaborating ...
ASIC Design Engineer
Austin, TX · On-site
$250/hr
As a Senior ASIC Design Engineer, you will take a leadership role in defining, implementing, and ... You will own the microarchitecture from high-level concept through RTL signoff, collaborating ...
Senior RTL Design Engineer
Austin, TX · On-site
$120K - $225K/yr
We're hiring experienced RTL Design Engineers to play a key role in designing and implementing the components that will bring our next-generation AI processors to life. About Us: Mythic is building ...
Senior RTL Design Engineer
Austin, TX · On-site
$120K - $225K/yr
We're hiring experienced RTL Design Engineers to play a key role in designing and implementing the components that will bring our next-generation AI processors to life. About Us: Mythic is building ...
Senior RTL Design Engineer
Austin, TX · On-site
$120K - $225K/yr
We're hiring experienced RTL Design Engineers to play a key role in designing and implementing the components that will bring our next-generation AI processors to life. About Us: Mythic is building ...
Quick apply
Senior RTL Design Engineer
Austin, TX · On-site
$120K - $225K/yr
We're hiring experienced RTL Design Engineers to play a key role in designing and implementing the components that will bring our next-generation AI processors to life. About Us: Mythic is building ...
ASIC Digital Design, Sr Staff Engineer - 18384
Austin, TX · On-site
$138K/yr
You bring strong RTL design and verification expertise to solve challenging ASIC design problems. * You enjoy collaborating across engineering teams to improve performance, power, quality, and ...
ASIC Digital Design, Sr Staff Engineer - 18384
Austin, TX · On-site
$138K/yr
You bring strong RTL design and verification expertise to solve challenging ASIC design problems. * You enjoy collaborating across engineering teams to improve performance, power, quality, and ...
Freelance Asic Rtl Design Engineer information
See Georgetown, TX salary details
$21.86 is the 25th percentile. Wages below this are outliers.
$13.85 - $23.76
31% of jobs
The median wage is $29.87 / hr.
$23.76 - $33.66
31% of jobs
$33.66 - $43.57
4% of jobs
$52.24 is the 75th percentile. Wages above this are outliers.
$43.57 - $53.48
10% of jobs
$53.48 - $63.39
9% of jobs
$63.39 - $73.30
5% of jobs
$73.30 - $83.21
0% of jobs
$83.21 - $93.12
8% of jobs
$93.12 - $103.02
0% of jobs
$103.02 - $112.93
0% of jobs
$112.93 - $122.84
1% of jobs
$13
$44
$122
How much do freelance asic rtl design engineer jobs pay per hour?
As of Sep 8, 2026, the average hourly pay for freelance asic rtl design engineer in Georgetown, TX is $44.33, according to ZipRecruiter salary data. Most workers in this role earn between $22.55 and $57.40 per hour, depending on experience, location, and employer.
Are freelance ASIC RTL design engineers in demand?
Freelance ASIC RTL design engineers are in demand due to the growing need for custom chip development in industries like telecommunications, AI, and consumer electronics. Skills in hardware description languages such as Verilog or VHDL, along with experience in FPGA prototyping, enhance employability in this flexible work arrangement.
How much does a Freelance ASIC RTL Design Engineer make?
Freelance ASIC RTL Design Engineers typically earn between $50 and $150 per hour, depending on experience, project complexity, and location. Rates can vary based on expertise in hardware description languages like Verilog or VHDL and familiarity with FPGA or ASIC design tools.
What job categories do people searching Freelance Asic Rtl Design Engineer jobs in Georgetown, TX look for?
The top searched job categories for Freelance Asic Rtl Design Engineer jobs in Georgetown, TX are:
What cities near Georgetown, TX are hiring for Freelance Asic Rtl Design Engineer jobs?
Cities near Georgetown, TX with the most Freelance Asic Rtl Design Engineer job openings:
Full-time
Posted 18 days ago
Job description
About the team About the role
The RTL design team builds the compute datapath, on-chip network, and memory subsystems inside SambaNova's RDU AI accelerator. Their work spans microarchitecture through tape-out: RTL implementation, PPA trade-offs, quality gates like lint, CDC, and LEC, and timing closure with
About the roleSambaNova RTL Design Engineers design component units of the Reconfigurable Dataflow Unit (RDU) ASICs behind our AI acceleration systems. You'll own blocks within a larger subsystem, contributing sections of the microarchitecture specification, writing and debugging the RTL, and carrying your blocks through implementation, tape-out, and silicon bring-up. You'll work alongside principal engineers, architects, design verification, and physical design, and take on larger blocks as you build depth in our architecture
Required Qualifications- B.S. in Electrical Engineering, Computer Engineering, or Computer Science
- 5+ years of experience in ASIC RTL design
- Solid foundation in computer architecture and digital logic design
- Strong SystemVerilog RTL design skills for high-speed, high-performance ASICs
- Experience making design decisions that trade off power, performance, and area
- Knowledge of industry-standard interconnects and protocols including AXI, PCIe, Ethernet, and HBM or DDR
- Experience with digital logic synthesis tools and static timing analysis
- Proficiency with industry-standard tools for linting, clock domain crossing, and logical equivalence checking
- Experience implementing SystemVerilog Assertions to check design intent
- Familiarity with tools and simulators for hardware performance analysis and tuning
- Familiarity with Git for managing release cycles
- Scripting skills in Python and Linux shell
- M.S. or Ph.D. in Electrical Engineering, Computer Engineering, or Computer Science
- Exposure to a full ASIC development cycle through tape-out and production silicon
- Interest in or knowledge of AI workload acceleration techniques
- Experience with low-power design techniques such as clock gating and DVFS at advanced process nodes
- Exposure to emulation or FPGA prototyping platforms for pre-silicon validation