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Freelance Asic Rtl Design Engineer Jobs in Georgetown, TX

Intel Corporation

CPU RTL Design Engineer

Austin, TX · On-site

$141K - $269K/yr

As a CPU Logic Design Engineer, you will play a critical role in designing and optimizing the logic for Intel's cutting-edge processors. You will drive the development of register transfer level (RTL ...

Meta

ASIC Engineer, Power

Austin, TX · On-site +1

$146K/yr

As an ASIC Engineer specializing in power on the EDA Infrastructure team, you will develop and ... Collaborate with RTL design, physical design, and verification teams to identify and resolve power ...

Meta

ASIC Engineer, Physical Design

Austin, TX

$178K/yr

ASIC Engineer, Physical Design Responsibilities: * Lead physical implementation of complex ASIC ... Collaborate with RTL design and architecture teams to provide physical design feedback on ...

Intel

Senior CPU RTL Design Engineer

Austin, TX

As a CPU RTL Logic Design Engineer your responsibilities will include but are not limited to: Collaborates, drives and develops logic design, register transfer level (RTL) coding, and simulation for ...

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Freelance Asic Rtl Design Engineer information

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How much do freelance asic rtl design engineer jobs pay per hour?

As of Aug 19, 2026, the average hourly pay for freelance asic rtl design engineer in Georgetown, TX is $44.33, according to ZipRecruiter salary data. Most workers in this role earn between $22.55 and $57.40 per hour, depending on experience, location, and employer.

Are freelance ASIC RTL design engineers in demand?

Freelance ASIC RTL design engineers are in demand due to the growing need for custom chip development in industries like telecommunications, AI, and consumer electronics. Skills in hardware description languages such as Verilog or VHDL, along with experience in FPGA prototyping, enhance employability in this flexible work arrangement.

How much does a Freelance ASIC RTL Design Engineer make?

Freelance ASIC RTL Design Engineers typically earn between $50 and $150 per hour, depending on experience, project complexity, and location. Rates can vary based on expertise in hardware description languages like Verilog or VHDL and familiarity with FPGA or ASIC design tools.

What job categories do people searching Freelance Asic Rtl Design Engineer jobs in Georgetown, TX look for?

The top searched job categories for Freelance Asic Rtl Design Engineer jobs in Georgetown, TX are:

What cities near Georgetown, TX are hiring for Freelance Asic Rtl Design Engineer jobs?

Cities near Georgetown, TX with the most Freelance Asic Rtl Design Engineer job openings:

Freelance Asic Rtl Design Engineer jobs near you

ASIC Implementation Engineer - Static Verification

Meta

Austin, TX

$114K/yr

Full-time

Re-posted 23 days ago

Meta rating

7.8

Company rating: 7.8 out of 10

Based on 45 frontline employees who took The Breakroom Quiz

137th of 245 rated software companies

Job description

Meta is hiring ASIC Frontend Implementation Engineers within our Infrastructure organization. We are looking for individuals with experience in front-end implementation from RTL to netlist, including RTL Lint, CDC analysis, timing constraints, synthesis to build efficient System on Chip (SoC) and IP for data center applications.
ASIC Implementation Engineer - Static Verification Responsibilities:
  • Perform Flat and Hierarchical Clock Domain Crossing and work with the designers to analyze the complex clock domain crossings and sign off the CDC
  • Perform Flat and Hierarchical Reset Domain crossing Checks. Understand the Reset-Architecture by working with Design and FW teams and develop reset groups and the corresponding reset sequence for RDC
  • Perform RTL Lint and work with the Designers to create waivers
  • Perform RTL DFT Analysis and improve the DFT coverage for Stuck-at faults
  • Run Logic/Physical Synthesis using advanced optimization techniques and generate optimized Gate Level Netlist for Timing, Area, Power
  • Developing Automation scripts and Methodology for all FE-tools including (Lint, CDC, RDC,)
  • Work closely with the Design Engineers, DV Engineers, Emulation Engineers in supporting them with the handoff tasks. Interact with Physical Design Engineers and provide them with timing/congestion feedback

Minimum Qualifications:
  • Currently has, or is in the process of obtaining a Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience. Degree must be completed prior to joining Meta
  • 2+ years of experience in static verification tools
  • Experience with Lint, Clock Domain & Reset Domain crossing
  • Experience with SOC CDC signoff
  • Knowledge of SOC Integration (Clocking, Reset, PLL, etc)
  • Knowledge of front-end ASIC flows
  • Experience with RTL design using SystemVerilog or other HDL
  • Experience with communicating across functional internal teams and vendors

Preferred Qualifications:
  • Experience with SOC Design Integration and Front-End Implementation
  • Experience with Netlist-CDC Analysis and improving MTBF
  • Knowledge of Timing/physical libraries, SRAM Memories
  • Scripting and programming experience using Perl/Python, TCL, and Make
  • Experience with developing structural rule based checks for RTL & Netlist
  • Experience with Design Compiler, Spyglass, PrimeTime, Formality or equivalent tools

About Meta:
Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today—beyond the constraints of screens, the limits of distance, and even the rules of physics.
Meta is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment.
Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at accommodations-ext@meta.com.
$114,000/year to $172,000/year + bonus + equity + benefits
Individual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate, monthly rate, or annual salary only, and do not include bonus, equity or sales incentives, if applicable. In addition to base compensation, Meta offers benefits. Learn more about benefits at Meta.

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