Semiconductor Design Engineer Jobs in Austin, TX

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We are seeking a CAD Engineering & Design Methodology Engineer to help develop and execute technical roadmaps for next-generation design tools, flows, and methodologies. This role will focus on enabling power-efficient, scalable GPU, CPU, and complex SoC designs across advanced semiconductor process nodes. The ideal candidate will have strong experience with CAD engineering, design methodology, low-power design, ASIC flows, and EDA tools, along with the ability to troubleshoot complex technical challenges and drive methodology improvements across design teams.

• Develop and execute technical roadmaps for CAD engineering, design enablement, and methodology improvements.
• Contribute to the development of next-generation tools, design flows, and methodologies for advanced GPU, CPU, and SoC designs.
• Develop robust automation solutions and troubleshoot complex CAD tools, design flows, and methodology issues.
• Promote consistent adoption of design best practices across engineering organizations.
• Support low-power design enablement at scale, including methodologies for: Power analysis Power optimization Power verification Power signoff.
• Collaborate closely with RTL, verification, physical design, and design-technology co-optimization (DTCO) teams.
• Partner with internal engineering organizations and external EDA vendors to leverage tool capabilities, resolve systemic design challenges, and improve technology readiness.
• Lead and contribute to moderate-to-complex technical projects from definition through implementation.
• Identify opportunities to improve design productivity, quality, scalability, and efficiency.
• Develop and maintain technical documentation, methodologies, and best practices.
• Stay current with emerging GPU, ASIC, verification, power, and semiconductor design technologies.

Bachelor's degree in Computer Science, Computer Engineering, Electrical Engineering, or a related technical field with 6+ years of relevant experience; or Master's degree with 4+ years of relevant experience; or Ph.D. with 2+ years of relevant experience. 6+ years of hands-on experience in CAD engineering, design methodology, or design enablement supporting GPU, CPU, or complex SoC programs. Strong working knowledge of low-power design tools and methodologies, including RTL- and gate-level power analysis, optimization, and signoff. Experience with tools such as PrimePower, PowerArtist, Empower, Joules, RTL-Architect, or equivalent technologies. Strong understanding of the end-to-end ASIC design flow, including: RTL design and verification Synthesis Physical design Timing analysis Power analysis and optimization EMIR analysis DTCO considerations Hands-on experience with CAD/EDA tools supporting simulation, synthesis, linting, and verification. Experience with major EDA platforms, such as Synopsys, Cadence, or Siemens EDA/Mentor Graphics. Hands-on experience with EMIR analysis tools and methodologies, including transistor-, gate-, and package-level analysis. Experience with tools such as RedHawk, Totem, Voltus, or equivalent. Strong analytical, troubleshooting, and problem-solving skills with a data-driven approach. Excellent communication and collaboration skills. Ability to navigate ambiguity, manage competing priorities, and maintain ownership in a fast-paced engineering environment.

• Experience supporting advanced-node semiconductor design programs.
• Background in GPU, CPU, or high-performance SoC architecture and implementation.
• Experience developing scalable CAD automation and design methodologies.
• Experience working directly with EDA vendors to evaluate, debug, and optimize tool capabilities.
• Strong understanding of power-performance-area (PPA) optimization and design-technology co-optimization.

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