DDR Design Engineer
Beaverton, OR · On-site
As a logic design engineer, you will be involved in all phases of the design, from concept study ... You will provide high-quality RTL description, including assertions, for the design. Use formal ...
DDR Design Engineer
Beaverton, OR · On-site
As a logic design engineer, you will be involved in all phases of the design, from concept study ... You will provide high-quality RTL description, including assertions, for the design. Use formal ...
Hardware Design Engineer
Hillsboro, OR · Hybrid
$106K - $198K/yr
RTL coding and verification * Memory Controller + PHY integration and verification * Customer ... Significant ASIC and/or FPGA design experience * Ability to learn quickly and work independently
Hardware Design Engineer
Hillsboro, OR · Hybrid
$106K - $198K/yr
RTL coding and verification * Memory Controller + PHY integration and verification * Customer ... Significant ASIC and/or FPGA design experience * Ability to learn quickly and work independently
As a logic design engineer, you will be involved in all phases of the design, from concept study ... You will provide high-quality RTL description, including assertions, for the design. Use formal ...
As a logic design engineer, you will be involved in all phases of the design, from concept study ... You will provide high-quality RTL description, including assertions, for the design. Use formal ...
Hardware Design Engineer
Hillsboro, OR · On-site
$106K - $198K/yr
RTL coding and verification * Memory Controller + PHY integration and verification * Customer ... Significant ASIC and/or FPGA design experience * Ability to learn quickly and work independently
Hardware Design Engineer
Hillsboro, OR · On-site
$106K - $198K/yr
RTL coding and verification * Memory Controller + PHY integration and verification * Customer ... Significant ASIC and/or FPGA design experience * Ability to learn quickly and work independently
FE RTL Infrastructure - CAD Engineer
$150K - $277K/yr
Description As a Front-End (FE) RTL Infrastructure - CAD Engineer, you will play a major role in developing and supporting a reliable infrastructure and work environments that design and verification ...
FE RTL Infrastructure - CAD Engineer
$150K - $277K/yr
Description As a Front-End (FE) RTL Infrastructure - CAD Engineer, you will play a major role in developing and supporting a reliable infrastructure and work environments that design and verification ...
Hardware Design Engineer
Hillsboro, OR · On-site
$106K - $198K/yr
RTL coding and verification * Memory Controller + PHY integration and verification * Customer ... Significant ASIC and/or FPGA design experience * Ability to learn quickly and work independently
Hardware Design Engineer
Hillsboro, OR · On-site
$106K - $198K/yr
RTL coding and verification * Memory Controller + PHY integration and verification * Customer ... Significant ASIC and/or FPGA design experience * Ability to learn quickly and work independently
FE RTL Infrastructure - CAD Engineer
$129K - $194K/yr
Description As a Front-End (FE) RTL Infrastructure - CAD Engineer, you will play a major role in developing and supporting a reliable infrastructure and work environments that design and verification ...
FE RTL Infrastructure - CAD Engineer
$129K - $194K/yr
Description As a Front-End (FE) RTL Infrastructure - CAD Engineer, you will play a major role in developing and supporting a reliable infrastructure and work environments that design and verification ...
FE RTL Infrastructure - CAD Engineer
$129K - $194K/yr
Description As a Front-End (FE) RTL Infrastructure - CAD Engineer, you will play a major role in developing and supporting a reliable infrastructure and work environments that design and verification ...
FE RTL Infrastructure - CAD Engineer
$129K - $194K/yr
Description As a Front-End (FE) RTL Infrastructure - CAD Engineer, you will play a major role in developing and supporting a reliable infrastructure and work environments that design and verification ...
FE RTL Infrastructure - CAD Engineer
$150K - $277K/yr
Description As a Front-End (FE) RTL Infrastructure - CAD Engineer, you will play a major role in developing and supporting a reliable infrastructure and work environments that design and verification ...
FE RTL Infrastructure - CAD Engineer
$150K - $277K/yr
Description As a Front-End (FE) RTL Infrastructure - CAD Engineer, you will play a major role in developing and supporting a reliable infrastructure and work environments that design and verification ...
RTL coding: Verilog / System Verilog * Master's degree or PHD in Electrical Engineering, Computer Engineering or equivalent. * 5+ years of experience with RTL Design * Good English skills ...
RTL coding: Verilog / System Verilog * Master's degree or PHD in Electrical Engineering, Computer Engineering or equivalent. * 5+ years of experience with RTL Design * Good English skills ...
Senior Engineer, Digital Design Engineering
Beaverton, OR · On-site
$121K - $174K/yr
... RTL, Standard cells, and similar approaches as necessary for both mixed signal ASIC and FPGA ... Digital Design Engineer or related occupation performing digital or mixed signal design and ...
Senior Engineer, Digital Design Engineering
Beaverton, OR · On-site
$121K - $174K/yr
... RTL, Standard cells, and similar approaches as necessary for both mixed signal ASIC and FPGA ... Digital Design Engineer or related occupation performing digital or mixed signal design and ...
Senior Engineer, Digital Design Engineering
Beaverton, OR · On-site
$121K - $174K/yr
... RTL, Standard cells, and similar approaches as necessary for both mixed signal ASIC and FPGA ... Digital Design Engineer or related occupation performing digital or mixed signal design and ...
Senior Engineer, Digital Design Engineering
Beaverton, OR · On-site
$121K - $174K/yr
... RTL, Standard cells, and similar approaches as necessary for both mixed signal ASIC and FPGA ... Digital Design Engineer or related occupation performing digital or mixed signal design and ...
Senior Engineer, Digital Design Engineering
$121K - $174K/yr
... RTL, Standard cells, and similar approaches as necessary for both mixed signal ASIC and FPGA ... Digital Design Engineer or related occupation performing digital or mixed signal design and ...
Senior Engineer, Digital Design Engineering
$121K - $174K/yr
... RTL, Standard cells, and similar approaches as necessary for both mixed signal ASIC and FPGA ... Digital Design Engineer or related occupation performing digital or mixed signal design and ...
The NVIDIA CPU team is looking for a top ASIC Engineer with an interest in SOC design automation, RTL integration, and chip build and assembly. You should be passionate about developing methodologies ...
The NVIDIA CPU team is looking for a top ASIC Engineer with an interest in SOC design automation, RTL integration, and chip build and assembly. You should be passionate about developing methodologies ...
The NVIDIA CPU team is looking for a top ASIC Engineer with an interest in SOC design automation, RTL integration, and chip build and assembly. You should be passionate about developing methodologies ...
The NVIDIA CPU team is looking for a top ASIC Engineer with an interest in SOC design automation, RTL integration, and chip build and assembly. You should be passionate about developing methodologies ...
We are now looking for a Senior Logic Design Engineer! As a member of our CPU Logic Design Team ... Verilog expertise required as is a deep understanding of ASIC design flow including RTL design ...
We are now looking for a Senior Logic Design Engineer! As a member of our CPU Logic Design Team ... Verilog expertise required as is a deep understanding of ASIC design flow including RTL design ...
SoC Logic Design Engineer
Hillsboro, OR · On-site
$141K - $232K/yr
Key Responsibilities - Develop high-quality logic designs, including Register Transfer Level (RTL ... Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom ...
SoC Logic Design Engineer
Hillsboro, OR · On-site
$141K - $232K/yr
Key Responsibilities - Develop high-quality logic designs, including Register Transfer Level (RTL ... Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom ...
Timing Design Engineer
Beaverton, OR · On-site
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... You will closely interact with RTL designer to understand design intent and clock structure, with ...
Timing Design Engineer
Beaverton, OR · On-site
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... You will closely interact with RTL designer to understand design intent and clock structure, with ...
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... You will closely interact with RTL designer to understand design intent and clock structure, with ...
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... You will closely interact with RTL designer to understand design intent and clock structure, with ...
Timing Design Engineer
Beaverton, OR · On-site
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... You will closely interact with RTL designer to understand design intent and clock structure, with ...
Timing Design Engineer
Beaverton, OR · On-site
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... You will closely interact with RTL designer to understand design intent and clock structure, with ...
Freelance Asic Rtl Design Engineer information
Are freelance ASIC RTL design engineers in demand?
Freelance ASIC RTL design engineers are in demand due to the growing need for custom chip development in industries like telecommunications, AI, and consumer electronics. Skills in hardware description languages such as Verilog or VHDL, along with experience in FPGA prototyping, enhance employability in this flexible work arrangement.
How much does a Freelance ASIC RTL Design Engineer make?
Freelance ASIC RTL Design Engineers typically earn between $50 and $150 per hour, depending on experience, project complexity, and location. Rates can vary based on expertise in hardware description languages like Verilog or VHDL and familiarity with FPGA or ASIC design tools.
What are the most commonly searched types of Asic Rtl Design Engineer jobs in Oregon?
The most popular types of Asic Rtl Design Engineer jobs in Oregon are:
What are popular job titles related to Freelance Asic Rtl Design Engineer jobs in Oregon?
For Freelance Asic Rtl Design Engineer jobs in Oregon, the most frequently searched job titles are:
What job categories do people searching Freelance Asic Rtl Design Engineer jobs in Oregon look for?
The top searched job categories for Freelance Asic Rtl Design Engineer jobs in Oregon are:
What cities in Oregon are hiring for Freelance Asic Rtl Design Engineer jobs?
Cities in Oregon with the most Freelance Asic Rtl Design Engineer job openings:
Apple rating
8.0
Based on 677 frontline employees who took The Breakroom Quiz
7th of 30 rated technology retailers
Job description
At Apple, we work every day to craft products that enrich people's lives. If you're passionate about taking on unsolved challenges, we have a great opportunity for a results-oriented and highly motivated DDR Design Engineer.
As a member of our dynamic group, you will have the rare and rewarding opportunity to craft upcoming products that will delight and inspire millions of Apple's customers every single day. You will join the DDR PHY design team. We provide best-in-class PHY designs for high-performance, low power applications. As a logic design engineer, you will be involved in all phases of the design, from concept study, architecture definition, design and verification, to silicon bring-up and characterization.
Description
In this role, you will be responsible for performing concept studies and providing direction in terms of performance, gate count and power for various digital designs. You will be responsible for writing detailed design specification and test plans in close collaboration with architecture, circuit designers and verification engineers. You will provide high-quality RTL description, including assertions, for the design. Use formal tools and static checkers to guarantee RTL quality. You will also support design verification to insure bug-free first silicon. Responsibilities will include driving functional and code coverage as well as timing closure for your designs and supporting silicon bring-up, performance and power characterization.
Minimum Qualifications
BS degree in technical discipline with minimum 10 years of relevant experience.
Preferred Qualifications
RTL design using Verilog or SystemVerilog, assertion writing.
Design of state machines, data paths, arbitration and clock domain crossing logic.
Logic synthesis, timing constraints.
Exposure to Design For Test, understanding of scan concept and writing DFT friendly RTL.
Unified Power Format for simulation, synthesis and electrical rule checking Equivalence checking.
Prior experience in DDR PHY design and mixed-signal environment is a plus.
As a member of our dynamic group, you will have the rare and rewarding opportunity to craft upcoming products that will delight and inspire millions of Apple's customers every single day. You will join the DDR PHY design team. We provide best-in-class PHY designs for high-performance, low power applications. As a logic design engineer, you will be involved in all phases of the design, from concept study, architecture definition, design and verification, to silicon bring-up and characterization.
Description
In this role, you will be responsible for performing concept studies and providing direction in terms of performance, gate count and power for various digital designs. You will be responsible for writing detailed design specification and test plans in close collaboration with architecture, circuit designers and verification engineers. You will provide high-quality RTL description, including assertions, for the design. Use formal tools and static checkers to guarantee RTL quality. You will also support design verification to insure bug-free first silicon. Responsibilities will include driving functional and code coverage as well as timing closure for your designs and supporting silicon bring-up, performance and power characterization.
Minimum Qualifications
BS degree in technical discipline with minimum 10 years of relevant experience.
Preferred Qualifications
RTL design using Verilog or SystemVerilog, assertion writing.
Design of state machines, data paths, arbitration and clock domain crossing logic.
Logic synthesis, timing constraints.
Exposure to Design For Test, understanding of scan concept and writing DFT friendly RTL.
Unified Power Format for simulation, synthesis and electrical rule checking Equivalence checking.
Prior experience in DDR PHY design and mixed-signal environment is a plus.
About Apple
Sourced by ZipRecruiter
Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it.
Industry
Computer and electronic product manufacturing
Company size
10,000+ Employees
Headquarters location
Cupertino, CA, US
Year founded
1976