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Entry Level Physical Design Engineer Jobs (NOW HIRING)

Mirafra Technology

Physical Design Engineer

San Diego, CA

$144K - $148K/yr

Physical Design Engineer Location : San Diego,CA Type : Full Time Job Overview: To do Floor planning, P&R, timing closure SI prevention/fixing, power planning, CTS, PV and I/R drop for Block as well ...

Scadea Solutions Inc

Physical Design Engineer

San Diego, CA · On-site

$144K - $148K/yr

PHYSICAL DESIGN Engineer Work Location -San Diego , CA Duration: 6+ Months Experience: 8-10Yrs Start Date- Immediate • Floor planning, P&R, timing closure SI prevention/fixing, power planning, CTS ...

Intelliswift Software

Physical Design Engineer

Phoenix, AZ · On-site

$135K - $139K/yr

Python Programming Language - * Physical Design Develop & own physical design implementation of multi-hierarchy low-power designs including physical-aware logic synthesis, design for testability ...

Ayar Labs

Engineer, Physical Design

San Jose, CA

$120K - $160K/yr

Physical Design Engineer: Location: San Jose (on-site) Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), we are using light ...

Ayar Labs

Engineer, Physical Design

San Jose, CA · On-site

$120K - $160K/yr

Physical Design Engineer: Location: San Jose (on-site) Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), we are using light ...

TSMC

Physical Design Engineer (7452)

San Jose, CA · On-site

$155K - $160K/yr

Overview of Role Are you a highly motivated and skilled Physical Design Engineer with at least 3 years of industrial experience eager to push the boundaries of semiconductor technology? Join our ...

TSMC

Physical Design Engineer (7452)

San Jose, CA · On-site

$155K - $160K/yr

Overview of Role Are you a highly motivated and skilled Physical Design Engineer with at least 3 years of industrial experience eager to push the boundaries of semiconductor technology? Join our ...

Qualcomm

Physical Design Engineer

San Diego, CA · On-site

$98K - $147K/yr

As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance ...

Embtel Inc

Physical Design Engineer (Remote)

Sunnyvale, CA · On-site

$159K - $164K/yr

Physical Design Engineer Locations : Sunnyvale, CA/Portland, OR (Remote) No. of positions: 11 Duration: 6+ Months Contract Role Solid experience in place & route flow (placement guidelines, clock ...

Intel

CPU Core Physical Design Engineer

Folsom, CA

$105K - $200K/yr

The CPU Physical Design Engineer: * Performs physical design implementation of custom CPU designs from RTL to GDS to create a design database that is ready for manufacturing. Conducts all aspects of ...

Intel Corporation

CPU Physical Design Engineer

Austin, TX · On-site

$134K - $138K/yr

Performs physical design implementation of custom CPU designs from RTL to GDS to create a design ... Bachelors in Computer Engineering or Electrical Engineering or related field with 2+ years of ...

Intel

CPU Physical Design Engineer

Austin, TX

$134K - $138K/yr

Performs physical design implementation of custom CPU designs from RTL to GDS to create a design ... Bachelors in Computer Engineering or Electrical Engineering or related field with 2+ years of ...

Apple

GPU Physical Design Engineer

Austin, TX

$147K - $272K/yr

This role requires a mix of strategic engineering along with hands-on experience in physical design and large chip integration, being responsible for implementing complete chip design from RTL to ...

Apple

GPU Physical Design Engineer

Austin, TX

$147K - $272K/yr

This role requires a mix of strategic engineering along with hands-on experience in physical design and large chip integration, being responsible for implementing complete chip design from RTL to ...

Apple

GPU Physical Design Engineer

Austin, TX · On-site

$147K - $272K/yr

This role requires a mix of strategic engineering along with hands-on experience in physical design and large chip integration, being responsible for implementing complete chip design from RTL to ...

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Entry Level Physical Design Engineer information

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$30K

$69.4K

$118K

How much do entry level physical design engineer jobs pay per year?

As of Jun 16, 2026, the average yearly pay for entry level physical design engineer in the United States is $69,362.00, according to ZipRecruiter salary data. Most workers in this role earn between $51,500.00 and $78,500.00 per year, depending on experience, location, and employer.

What does an Entry Level Physical Design Engineer do?

An Entry Level Physical Design Engineer works on the layout and implementation of integrated circuits (ICs), specifically focusing on translating logical circuit designs into physical layouts that can be manufactured. Their responsibilities often include tasks such as floorplanning, placement, routing, timing analysis, and design rule checking using specialized software tools. They collaborate with other engineers to ensure that the chip meets performance, power, and area requirements. Entry-level engineers are typically involved in supporting more experienced team members while learning industry-standard design flows and tools. This role plays a crucial part in bringing new electronic products to market.

What are some common challenges Entry Level Physical Design Engineers face when transitioning from academic projects to industry roles?

Entry Level Physical Design Engineers often find that real-world projects are larger in scale and complexity compared to academic assignments. Adapting to industry-standard tools like Cadence or Synopsys, managing strict deadlines, and collaborating within multidisciplinary teams can be challenging at first. Additionally, understanding and following established workflows, as well as dealing with the nuances of process technology and design constraints, require a steep learning curve. However, many companies provide mentorship and training to help new engineers integrate smoothly and develop their expertise.

What are the key skills and qualifications needed to thrive as an Entry Level Physical Design Engineer, and why are they important?

To thrive as an Entry Level Physical Design Engineer, you need a solid background in electrical engineering, digital logic design, and VLSI concepts, typically supported by a relevant bachelor’s or master’s degree. Familiarity with industry-standard tools like Cadence, Synopsys, or Mentor Graphics for layout, synthesis, and verification, as well as scripting languages such as TCL or Python, is essential. Strong problem-solving, teamwork, and attention to detail are standout soft skills for this role. These skills ensure the efficient translation of circuit designs into manufacturable layouts, driving successful chip development and collaboration in complex engineering environments.

What is the difference between Entry Level Physical Design Engineer vs Digital IC Design Engineer?

AspectEntry Level Physical Design EngineerDigital IC Design Engineer
CredentialsBachelor's in Electrical Engineering or Computer EngineeringBachelor's or Master's in Electrical Engineering or Computer Engineering
Work EnvironmentDesign teams, CAD tools, chip fabrication facilitiesDesign teams, simulation tools, hardware labs
Industry UsageFoundries, semiconductor companies, EDA firmsSemiconductor companies, integrated circuit design firms
Common Search IntentEntry level, physical implementation, chip layoutDigital logic, circuit design, RTL coding

Entry Level Physical Design Engineers focus on translating digital circuit designs into physical layouts, ensuring manufacturability and performance. Digital IC Design Engineers primarily work on designing digital circuits at the RTL level. While both roles require a background in electrical engineering and involve working with semiconductor companies, physical design emphasizes layout and fabrication, whereas digital design emphasizes circuit functionality and logic.

More about Entry Level Physical Design Engineer jobs
What cities are hiring for Entry Level Physical Design Engineer jobs? Cities with the most Entry Level Physical Design Engineer job openings:
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What job categories do people searching Entry Level Physical Design Engineer jobs look for? The top searched job categories for Entry Level Physical Design Engineer jobs are:
Entry Level Physical Design Engineer jobs near you
Infographic showing various Entry Level Physical Design Engineer job openings in the United States as of June 2026, with employment types broken down into 100% Full Time. Highlights an 100% In-person job distribution, with an average salary of $69,362 per year, or $33.3 per hour.

Physical Design Engineer

Mirafra Technology

San Diego, CA

$144K - $148K/yr

Full-time

Posted 7 days ago

Job description

Company Description

About Mirafra :
Mirafra is software service base organization started in 2004.

     We are 500+ employees in India and 250+ In US
    Clear visibility to senior management which helps for constant professional growth

Job Description

Title : Physical Design Engineer
Location : San Diego,CA
Type : Full Time 


Job Overview:
To do Floor planning, P&R, timing closure SI prevention/fixing, power planning, CTS, PV and I/R drop for Block as well as Top level MSM. Work On PD projects.

Minimum Qualifications:
Able to deal with MSM Top level complexity from FP, Placement, CTS, Routing and timing closure Must be able to take the Hardmacro through P&R from Netlist to GDS including timing closure, formal and Physical verification.

Tools: EDA Physical design tools experience ( Examples: Cadence Innovas,
Synopsys ICC2, PrimetimeSi/Calibre/ etc)


Skills: Physical design implementation expertize in latest technology nodes in one of the below
domains or all of these.

1.Floor planning at Full chip level or Macro or Block Level a.Macro placement, power grid implementation, power routing, special routing like analog signals etc

b.Power collapse/Low power implementation flow

2.P&R: Place and route at chip level or block level, perform placement, timing closure in P&R mode, perform clock tree synthesis , routing etc

3.Timing closure/STA

a.Perform STA using primetime Si or Tempus or any industry standard STA engine, timing closure, ECO generation, timing correlation

b.Deep understanding of timing skills to perform correlation, timing fixes , corner/voltage definetions etc

4.Clock Tree Synthesis:

a.Perform custom or regular clock tree implementation at block level or top level.

b.Clock tree balance of complicated tree, clock power reduction
techniques etc

5.Low Power Implementation

a.Power collapse/power gaing techniques/implementation

b.UPF/CPF flow knowledge

c.CLP/FV

6. Physical Verification Using Calibre a.Running all the PV checks (DRc/LVS/ERC/Softcheck ) and deep understanding of all the rules and fixes
7. Perl/Python/Shell script experience is also preferred to help with automation

Additional Information

All your information will be kept confidential according to EEO guidelines.

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