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Entry Level Design Verification Engineer Jobs in Oregon

Apple

Timing Design Engineer

Beaverton, OR

... ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC design in terms of ... You will also come up with ideas and plans to verify your own timing constraints. You will innovate ...

Apple

Custom Circuits Design Engineer

Beaverton, OR

$150K - $277K/yr

You and your team will apply engineering fundamentals and start from scratch if needed, bringing ... verification and silicon bring up. - Work closely with layout team to complete the design and ...

Apple

Custom Circuits Design Engineer

Beaverton, OR

$150K - $277K/yr

You and your team will apply engineering fundamentals and start from scratch if needed, bringing ... verification and silicon bring up. - Work closely with layout team to complete the design and ...

Marmon

Product Development Engineer 2

Hillsboro, OR · On-site

Lead engineering deliverables for small projects or portions of larger projects within Product ... design verification and validation, design reviews, and associated testing. * Evaluate designs ...

Apple

FE RTL Infrastructure - CAD Engineer

Beaverton, OR · On-site

$172K/yr

In this role, you will support RTL gatekeeping infrastructure of design and verification collateral ... The FE RTL Infrastructure - CAD Engineer plays a key role in promoting and driving robust, scalable ...

Apple

FE RTL Infrastructure - CAD Engineer

Beaverton, OR · On-site

$172K/yr

In this role, you will support RTL gatekeeping infrastructure of design and verification collateral ... The FE RTL Infrastructure - CAD Engineer plays a key role in promoting and driving robust, scalable ...

Apple

FE RTL Infrastructure - CAD Engineer

Beaverton, OR

$129K - $194K/yr

In this role, you will support RTL gatekeeping infrastructure of design and verification collateral ... The FE RTL Infrastructure - CAD Engineer plays a key role in promoting and driving robust, scalable ...

Apple

FE RTL Infrastructure - CAD Engineer

Beaverton, OR

$150K - $277K/yr

In this role, you will support RTL gatekeeping infrastructure of design and verification collateral ... The FE RTL Infrastructure - CAD Engineer plays a key role in promoting and driving robust, scalable ...

Apple

FE RTL Infrastructure - CAD Engineer

Beaverton, OR

$129K - $194K/yr

In this role, you will support RTL gatekeeping infrastructure of design and verification collateral ... The FE RTL Infrastructure - CAD Engineer plays a key role in promoting and driving robust, scalable ...

Apple

FE RTL Infrastructure - CAD Engineer

Beaverton, OR

$150K - $277K/yr

In this role, you will support RTL gatekeeping infrastructure of design and verification collateral ... The FE RTL Infrastructure - CAD Engineer plays a key role in promoting and driving robust, scalable ...

Noralogic Inc

Structural Design Engineer

Hillsboro, OR · On-site

Structural Design Job Location: Hillsboro, OR Job Type: Fulltime The resource is expected to work ... This will also include, but not be limited to, meeting timing, performance verification, power ...

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Entry Level Design Verification Engineer information

See Oregon salary details

$111.5K

$157.7K

$176.6K

How much do entry level design verification engineer jobs pay per year?

As of Jul 7, 2026, the average yearly pay for entry level design verification engineer in Oregon is $157,694.00, according to ZipRecruiter salary data. Most workers in this role earn between $143,800.00 and $175,500.00 per year, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive in the Entry Level Design Verification Engineer position, and why are they important?

To thrive as an Entry Level Design Verification Engineer, you need a solid understanding of digital logic design, computer architecture, and verification methodologies, typically supported by a degree in electrical engineering, computer engineering, or a related field. Familiarity with hardware description languages (such as Verilog or VHDL), simulation tools, and industry-standard verification frameworks is essential. Strong analytical skills, attention to detail, and effective communication are vital soft skills for diagnosing issues and collaborating with design teams. These skills ensure accurate verification of hardware designs and smooth integration within the broader engineering workflow.

What is an Entry Level Design Verification Engineer job?

An Entry Level Design Verification Engineer ensures that hardware designs function correctly before production. They write and run testbenches using languages like SystemVerilog and work with simulation tools to verify chip functionality. Their role involves debugging, analyzing test results, and collaborating with designers to refine designs. This position is crucial in the semiconductor industry to prevent costly design errors. Typically, they work with verification methodologies like UVM to create efficient and reusable test environments.

What are typical tasks and responsibilities for an Entry Level Design Verification Engineer on a daily basis?

As an Entry Level Design Verification Engineer, your daily activities often include writing and executing testbenches, analyzing simulation results, identifying design bugs, and collaborating closely with design and development engineers to resolve issues. You may also be responsible for maintaining verification documentation and participating in code reviews or team meetings. The role involves a mix of hands-on technical work and teamwork, allowing you to learn best practices from experienced colleagues. Over time, you'll have opportunities to take on more complex verification tasks and contribute to process improvements as you gain experience.

What are popular job titles related to Entry Level Design Verification Engineer jobs in Oregon? For Entry Level Design Verification Engineer jobs in Oregon, the most frequently searched job titles are:
What job categories do people searching Entry Level Design Verification Engineer jobs in Oregon look for? The top searched job categories for Entry Level Design Verification Engineer jobs in Oregon are:
What cities in Oregon are hiring for Entry Level Design Verification Engineer jobs? Cities in Oregon with the most Entry Level Design Verification Engineer job openings:
Entry Level Design Verification Engineer jobs near you
Infographic showing various Entry Level Design Verification Engineer job openings in Oregon as of July 2026, with employment types broken down into 88% Full Time, 9% Part Time, 2% Contract, and 1% Nights. Highlights an 87% Physical, 3% Hybrid, and 10% Remote job distribution, with an average salary of $157,694 per year, or $75.8 per hour.
Timing Design Engineer

Timing Design Engineer

Apple

Beaverton, OR

Full-time

Posted 12 days ago

Apple rating

8.1

Company rating: 8.1 out of 10

Based on 667 frontline employees who took The Breakroom Quiz

5th of 30 rated technology retailers

Job description

Apple is where individual imaginations gather together, committing to the values that lead to great work. Every new product we build, service we create, or Apple Store experience we deliver is the result of us making each other’s ideas stronger. That happens because every one of us shares a belief that we can make something wonderful and share it with the world, changing lives for the better. It’s the diversity of our people and their thinking that inspires the innovation that runs through everything we do. When we bring everybody in, we can do the best work of our lives. Here, you’ll do more than join something - you’ll add something.
Description
As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC design in terms of timing. Key responsibilities include timing sign-off, STA and sign-off flow development, ownership of IP and block level timing constraints both for regular and custom timing requirements from synthesis to sign-off to achieve sign-off quality timing constraints. You will closely interact with RTL designer to understand design intent and clock structure, with CAD to understand and develop flow, and with Physical design team to close and sign-off timing. You will also come up with ideas and plans to verify your own timing constraints. You will innovate timing constraints and flow to facilitate timing closure and any potential pessimism or fall outs in timing analysis.
Preferred Qualifications
Proven knowledge of the ASIC design timing closure flow and methodology.
2+ years of experience in writing ASIC timing constraints and timing closure.
Expertise in STA tools (Primetime) and flow, knowledge of timing corners/modes, process variations and signal integrity related issues.
Hands on experience in timing/SDC constraints generation and management.
Proficient in scripting languages (Tcl and Perl).
Familiarity with synthesis, DFT and backend related methodology and tools.
Strong communication skills are a pre-requisite - you will be collaborating with many diverse groups at Apple.
The ideal candidate will be a self-starter and highly motivated to be successful at Apple.
Minimum Qualifications
Bachelors of Science in Electrical Engineering.

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About Apple

Sourced by ZipRecruiter

Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it.

Industry

Computer and electronic product manufacturing

Company size

10,000+ Employees

Headquarters location

Cupertino, CA, US

Year founded

1976

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