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Entry Level Design Verification Engineer Jobs in Oregon

... verification is a plus Possess data parsing, analysis and representation/plotting skills Minimum Qualifications Minimum BS and 10+ years of relevant experience Experience with a static timing ...

... verification is a plus Possess data parsing, analysis and representation/plotting skills Minimum Qualifications Minimum BS and 10+ years of relevant experience Experience with a static timing ...

... verification is a plus Possess data parsing, analysis and representation/plotting skills Minimum Qualifications Minimum BS and 10+ years of relevant experience Experience with a static timing ...

... verification is a plus Possess data parsing, analysis and representation/plotting skills Minimum Qualifications Minimum BS and 10+ years of relevant experience Experience with a static timing ...

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Entry Level Design Verification Engineer information

See Oregon salary details

$111.5K

$157.7K

$176.6K

How much do entry level design verification engineer jobs pay per year?

As of Jul 13, 2026, the average yearly pay for entry level design verification engineer in Oregon is $157,694.00, according to ZipRecruiter salary data. Most workers in this role earn between $143,800.00 and $175,500.00 per year, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive in the Entry Level Design Verification Engineer position, and why are they important?

To thrive as an Entry Level Design Verification Engineer, you need a solid understanding of digital logic design, computer architecture, and verification methodologies, typically supported by a degree in electrical engineering, computer engineering, or a related field. Familiarity with hardware description languages (such as Verilog or VHDL), simulation tools, and industry-standard verification frameworks is essential. Strong analytical skills, attention to detail, and effective communication are vital soft skills for diagnosing issues and collaborating with design teams. These skills ensure accurate verification of hardware designs and smooth integration within the broader engineering workflow.

What is an Entry Level Design Verification Engineer job?

An Entry Level Design Verification Engineer ensures that hardware designs function correctly before production. They write and run testbenches using languages like SystemVerilog and work with simulation tools to verify chip functionality. Their role involves debugging, analyzing test results, and collaborating with designers to refine designs. This position is crucial in the semiconductor industry to prevent costly design errors. Typically, they work with verification methodologies like UVM to create efficient and reusable test environments.

What are typical tasks and responsibilities for an Entry Level Design Verification Engineer on a daily basis?

As an Entry Level Design Verification Engineer, your daily activities often include writing and executing testbenches, analyzing simulation results, identifying design bugs, and collaborating closely with design and development engineers to resolve issues. You may also be responsible for maintaining verification documentation and participating in code reviews or team meetings. The role involves a mix of hands-on technical work and teamwork, allowing you to learn best practices from experienced colleagues. Over time, you'll have opportunities to take on more complex verification tasks and contribute to process improvements as you gain experience.

What are popular job titles related to Entry Level Design Verification Engineer jobs in Oregon? For Entry Level Design Verification Engineer jobs in Oregon, the most frequently searched job titles are:
What job categories do people searching Entry Level Design Verification Engineer jobs in Oregon look for? The top searched job categories for Entry Level Design Verification Engineer jobs in Oregon are:
What cities in Oregon are hiring for Entry Level Design Verification Engineer jobs? Cities in Oregon with the most Entry Level Design Verification Engineer job openings:
Infographic showing various Entry Level Design Verification Engineer job openings in Oregon as of July 2026, with employment types broken down into 88% Full Time, 9% Part Time, 2% Contract, and 1% Nights. Highlights an 87% Physical, 3% Hybrid, and 10% Remote job distribution, with an average salary of $157,694 per year, or $75.8 per hour.
Structural Design Engineer

Structural Design Engineer

Noralogic Inc

Hillsboro, OR

Full-time

Re-posted 23 days ago


Job description

Job Description

Job Title: Structural Design

Job Location: Hillsboro, OR

Job Type: Fulltime

Job Description:


The resource is expected to work on structural design. This work will be mainly in the synthesis and auto place and route (APR) areas. The CW team will take all of the required input files and scripts needed to run through the synthesis (RTL to netlist) and APR flows from floorplan to converged layout. This will also include, but not be limited to, meeting timing, performance verification, power, quality (DRC) and layout requirements ( verification/LVS). This may also include work that will come from other projects.

- Using industry standard tools and flows for RTL to Silicon Design and Verification e.g. ICC, Primetime.

- Structural design techniques related to synthesis, place & route, CTS, timing convergence, layout closure, UPF based power methodology, etc.

- Automation skill and Proficiency in scripting languages such as Perl/Tcl + added advantage

Regards,

Ajay Kumar

Noralogic Inc

307-316-1855

Qualifications

RTL, NOISE ANALYSIS, SYNTHESIS, CC1, RTL, TIMING, LAYOUT, LVS, VERIFICATION

Additional Information

All your information will be kept confidential according to EEO guidelines.