As part of our Digital Design Engineering group, you'll take imaginative and revolutionary ideas ... Familiar with tapeout of partitions and Verification Flows like LEQ, IR/EM, Timing and DFM closure ...
As part of our Digital Design Engineering group, you'll take imaginative and revolutionary ideas ... Familiar with tapeout of partitions and Verification Flows like LEQ, IR/EM, Timing and DFM closure ...
CPU Cache Microarchitect/RTL Engineer
$181K - $318K/yr
... design to target power, performance, area and timing goals • Verification - support the ... engineering team to implement and verify physical design on the aspects of timing, area ...
CPU Cache Microarchitect/RTL Engineer
$181K - $318K/yr
... design to target power, performance, area and timing goals • Verification - support the ... engineering team to implement and verify physical design on the aspects of timing, area ...
CPU Cache Microarchitect/RTL Engineer
$181K - $318K/yr
... design to target power, performance, area and timing goals • Verification - support the ... engineering team to implement and verify physical design on the aspects of timing, area ...
CPU Cache Microarchitect/RTL Engineer
$181K - $318K/yr
... design to target power, performance, area and timing goals • Verification - support the ... engineering team to implement and verify physical design on the aspects of timing, area ...
CPU Cache Microarchitect/RTL Engineer
$181K - $318K/yr
... design to target power, performance, area and timing goals • Verification - support the ... engineering team to implement and verify physical design on the aspects of timing, area ...
CPU Cache Microarchitect/RTL Engineer
$181K - $318K/yr
... design to target power, performance, area and timing goals • Verification - support the ... engineering team to implement and verify physical design on the aspects of timing, area ...
Civil Engineer - Entry
Portland, OR · On-site
You will be a Civil Designer responsible for site design of commercial building projects, including ... A Bachelor's Degree in Civil Engineering with EIT registration is required to apply for this ...
Civil Engineer - Entry
Portland, OR · On-site
You will be a Civil Designer responsible for site design of commercial building projects, including ... A Bachelor's Degree in Civil Engineering with EIT registration is required to apply for this ...
CPU Cache Microarchitect/RTL Engineer
$181K - $318K/yr
... design to target power, performance, area and timing goals • Verification - support the ... engineering team to implement and verify physical design on the aspects of timing, area ...
CPU Cache Microarchitect/RTL Engineer
$181K - $318K/yr
... design to target power, performance, area and timing goals • Verification - support the ... engineering team to implement and verify physical design on the aspects of timing, area ...
CPU Cache Microarchitect/RTL Engineer
$181K - $318K/yr
... design to target power, performance, area and timing goals • Verification - support the ... engineering team to implement and verify physical design on the aspects of timing, area ...
CPU Cache Microarchitect/RTL Engineer
$181K - $318K/yr
... design to target power, performance, area and timing goals • Verification - support the ... engineering team to implement and verify physical design on the aspects of timing, area ...
CPU Cache Microarchitect/RTL Engineer
$181K - $318K/yr
... design to target power, performance, area and timing goals • Verification - support the ... engineering team to implement and verify physical design on the aspects of timing, area ...
CPU Cache Microarchitect/RTL Engineer
$181K - $318K/yr
... design to target power, performance, area and timing goals • Verification - support the ... engineering team to implement and verify physical design on the aspects of timing, area ...
Civil Engineer - Entry
Portland, OR · On-site
You will be a Civil Designer responsible for site design of commercial building projects, including ... A Bachelor's Degree in Civil Engineering with EIT registration is required to apply for this ...
Quick apply
Civil Engineer - Entry
Portland, OR · On-site
You will be a Civil Designer responsible for site design of commercial building projects, including ... A Bachelor's Degree in Civil Engineering with EIT registration is required to apply for this ...
Entry-Level Java Developer We are looking for multiple motivated and detail-oriented Entry-Level ... Design and implement RESTful Microservices for distributed systems * Collaborate with DevOps teams ...
Entry-Level Java Developer We are looking for multiple motivated and detail-oriented Entry-Level ... Design and implement RESTful Microservices for distributed systems * Collaborate with DevOps teams ...
OR · Hybrid
We are now looking for a motivated Circuit Design Engineer to join our dynamic and growing team. If ... Experience with RTL, logic synthesis and verification, knowledge of Place and Route, and ...
CPU Power Management Microarchitect/RTL Engineer
$181K - $318K/yr
... design to target power, performance, area and timing goals • Verification - support the ... engineering team to implement and verify physical design on the aspects of timing, area ...
CPU Power Management Microarchitect/RTL Engineer
$181K - $318K/yr
... design to target power, performance, area and timing goals • Verification - support the ... engineering team to implement and verify physical design on the aspects of timing, area ...
CPU Power Management Microarchitect/RTL Engineer
$181K - $318K/yr
... design to target power, performance, area and timing goals • Verification - support the ... engineering team to implement and verify physical design on the aspects of timing, area ...
CPU Power Management Microarchitect/RTL Engineer
$181K - $318K/yr
... design to target power, performance, area and timing goals • Verification - support the ... engineering team to implement and verify physical design on the aspects of timing, area ...
CPU Power Management Microarchitect/RTL Engineer
$181K - $318K/yr
... design to target power, performance, area and timing goals • Verification - support the ... engineering team to implement and verify physical design on the aspects of timing, area ...
CPU Power Management Microarchitect/RTL Engineer
$181K - $318K/yr
... design to target power, performance, area and timing goals • Verification - support the ... engineering team to implement and verify physical design on the aspects of timing, area ...
CPU Power Management Microarchitect/RTL Engineer
$181K - $318K/yr
... design to target power, performance, area and timing goals • Verification - support the ... engineering team to implement and verify physical design on the aspects of timing, area ...
CPU Power Management Microarchitect/RTL Engineer
$181K - $318K/yr
... design to target power, performance, area and timing goals • Verification - support the ... engineering team to implement and verify physical design on the aspects of timing, area ...
CPU Power Management Microarchitect/RTL Engineer
$181K - $318K/yr
... design to target power, performance, area and timing goals • Verification - support the ... engineering team to implement and verify physical design on the aspects of timing, area ...
CPU Power Management Microarchitect/RTL Engineer
$181K - $318K/yr
... design to target power, performance, area and timing goals • Verification - support the ... engineering team to implement and verify physical design on the aspects of timing, area ...
CPU Power Management Microarchitect/RTL Engineer
$181K - $318K/yr
... design to target power, performance, area and timing goals • Verification - support the ... engineering team to implement and verify physical design on the aspects of timing, area ...
CPU Power Management Microarchitect/RTL Engineer
$181K - $318K/yr
... design to target power, performance, area and timing goals • Verification - support the ... engineering team to implement and verify physical design on the aspects of timing, area ...
CPU CDC/RDC/STA Engineer
$181K - $318K/yr
As a CPU CDC/RDC/STA Engineer, you will play a major role analyzing the design and driving fixes as ... RTL, Verification, CAD, and Physical Design teams Preferred Qualifications Experience in ...
CPU CDC/RDC/STA Engineer
$181K - $318K/yr
As a CPU CDC/RDC/STA Engineer, you will play a major role analyzing the design and driving fixes as ... RTL, Verification, CAD, and Physical Design teams Preferred Qualifications Experience in ...
CPU CDC/RDC/STA Engineer
$181K - $318K/yr
As a CPU CDC/RDC/STA Engineer, you will play a major role analyzing the design and driving fixes as ... RTL, Verification, CAD, and Physical Design teams Preferred Qualifications Experience in ...
CPU CDC/RDC/STA Engineer
$181K - $318K/yr
As a CPU CDC/RDC/STA Engineer, you will play a major role analyzing the design and driving fixes as ... RTL, Verification, CAD, and Physical Design teams Preferred Qualifications Experience in ...
Civil Engineer - Entry Level
$65K - $84K/yr
Job Responsibilities * Assist with the planning, design and permitting of civil engineering, land development and infrastructure projects; * Assist with the preparation and modification of various ...
Civil Engineer - Entry Level
$65K - $84K/yr
Job Responsibilities * Assist with the planning, design and permitting of civil engineering, land development and infrastructure projects; * Assist with the preparation and modification of various ...
Entry Level Design Verification Engineer information
See Oregon salary details
$111.5K - $117.5K
0% of jobs
$117.5K - $123.4K
0% of jobs
$123.4K - $129.3K
0% of jobs
$129.3K - $135.2K
0% of jobs
$135.2K - $141.1K
0% of jobs
$143.4K is the 25th percentile. Wages below this are outliers.
$141.1K - $147K
65% of jobs
$147K - $152.9K
0% of jobs
$152.9K - $158.8K
0% of jobs
$158.8K - $164.7K
0% of jobs
$164.7K - $170.7K
0% of jobs
$172.3K is the 75th percentile. Wages above this are outliers.
$170.7K - $176.6K
35% of jobs
$111.5K
$157.7K
$176.6K
How much do entry level design verification engineer jobs pay per year?
As of Jun 10, 2026, the average yearly pay for entry level design verification engineer in Oregon is $157,694.00, according to ZipRecruiter salary data. Most workers in this role earn between $143,800.00 and $175,500.00 per year, depending on experience, location, and employer.
What are the key skills and qualifications needed to thrive in the Entry Level Design Verification Engineer position, and why are they important?
To thrive as an Entry Level Design Verification Engineer, you need a solid understanding of digital logic design, computer architecture, and verification methodologies, typically supported by a degree in electrical engineering, computer engineering, or a related field. Familiarity with hardware description languages (such as Verilog or VHDL), simulation tools, and industry-standard verification frameworks is essential. Strong analytical skills, attention to detail, and effective communication are vital soft skills for diagnosing issues and collaborating with design teams. These skills ensure accurate verification of hardware designs and smooth integration within the broader engineering workflow.
What is an Entry Level Design Verification Engineer job?
An Entry Level Design Verification Engineer ensures that hardware designs function correctly before production. They write and run testbenches using languages like SystemVerilog and work with simulation tools to verify chip functionality. Their role involves debugging, analyzing test results, and collaborating with designers to refine designs. This position is crucial in the semiconductor industry to prevent costly design errors. Typically, they work with verification methodologies like UVM to create efficient and reusable test environments.
What are typical tasks and responsibilities for an Entry Level Design Verification Engineer on a daily basis?
As an Entry Level Design Verification Engineer, your daily activities often include writing and executing testbenches, analyzing simulation results, identifying design bugs, and collaborating closely with design and development engineers to resolve issues. You may also be responsible for maintaining verification documentation and participating in code reviews or team meetings. The role involves a mix of hands-on technical work and teamwork, allowing you to learn best practices from experienced colleagues. Over time, you'll have opportunities to take on more complex verification tasks and contribute to process improvements as you gain experience.
What are popular job titles related to Entry Level Design Verification Engineer jobs in Oregon? For Entry Level Design Verification Engineer jobs in Oregon, the most frequently searched job titles are:
What job categories do people searching Entry Level Design Verification Engineer jobs in Oregon look for? The top searched job categories for Entry Level Design Verification Engineer jobs in Oregon are:
What cities in Oregon are hiring for Entry Level Design Verification Engineer jobs? Cities in Oregon with the most Entry Level Design Verification Engineer job openings:
$141K - $258K/yr
Part-time
Medical, Dental, Retirement
Posted 6 days ago
Apple rating
8.1
Based on 661 frontline employees who took The Breakroom Quiz
6th of 30 rated technology retailers
Job description
Do you have a passion for crafting entirely new solutions? As part of our Digital Design Engineering group, you’ll take imaginative and revolutionary ideas and determine how to turn them into reality! You and your team will apply engineering fundamentals and start from scratch if needed, bringing forward-thinking ideas to the real world. Your efforts will be groundbreaking. Your efforts will be groundbreaking. Join us, and you’ll help design the tools that allow us to bring customers experiences they’ve never before envisioned! We have an extraordinary opportunity for Physical Design Engineers. In this highly visible role, you will be at the heart of a processor design effort, working with foundation IP developers on silicon validation, making a critical impact delivering products to market quickly.
Description
Imagine yourself at the center of our SOC design effort, collaborating with all fields, playing a strategic role of getting functional products to millions of customers quickly. You will have the opportunity to integrate and come-up with new insights, as well as work with a team of hardworking engineers. As a Physical Design Engineer, you will be responsible for fully comprehensive library EDA view validation, by taking a P&R block through RTL to GDS steps. This will include physical synthesis, placement, CTS, routing, timing optimization, leakage recovery and closure & signoff. You will also be responsible for PT/spice correlation, signal and power EM analysis, IR analysis and PDV. You will also architect and compose blocks consisting of library cells for complete Silicon Validation.
Preferred Qualifications
We are looking for applicants with 2+ years of proven experience and strong understanding of the RTL2GDSII flow and concepts related to synthesis, place & route, CTS, timing convergence, layout closure.
Familiar with development of block/partitions for silicon validation of foundation Ips.
Familiar with ASIC integration flows, including power distribution, global signal planning, I/O planning and hard IP integration is a strong plus.
Familiar with tapeout of partitions and Verification Flows like LEQ, IR/EM, Timing and DFM closure is a strong plus.
Hands-on experience with ECO implementation, both functional and timing closure is a strong plus.
Familiar with DFT insertion, and multi-mode timing constraints is a strong plus.
Strong scripting skills using Perl/Tcl.
Strong written/verbal communication skills.
Minimum Qualifications
BS and a minimum of 2 years of relevant industry experience.
Pay & Benefits
At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $141,800 and $258,600, and your base pay will depend on your skills, qualifications, experience, and location.
Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
Description
Imagine yourself at the center of our SOC design effort, collaborating with all fields, playing a strategic role of getting functional products to millions of customers quickly. You will have the opportunity to integrate and come-up with new insights, as well as work with a team of hardworking engineers. As a Physical Design Engineer, you will be responsible for fully comprehensive library EDA view validation, by taking a P&R block through RTL to GDS steps. This will include physical synthesis, placement, CTS, routing, timing optimization, leakage recovery and closure & signoff. You will also be responsible for PT/spice correlation, signal and power EM analysis, IR analysis and PDV. You will also architect and compose blocks consisting of library cells for complete Silicon Validation.
Preferred Qualifications
We are looking for applicants with 2+ years of proven experience and strong understanding of the RTL2GDSII flow and concepts related to synthesis, place & route, CTS, timing convergence, layout closure.
Familiar with development of block/partitions for silicon validation of foundation Ips.
Familiar with ASIC integration flows, including power distribution, global signal planning, I/O planning and hard IP integration is a strong plus.
Familiar with tapeout of partitions and Verification Flows like LEQ, IR/EM, Timing and DFM closure is a strong plus.
Hands-on experience with ECO implementation, both functional and timing closure is a strong plus.
Familiar with DFT insertion, and multi-mode timing constraints is a strong plus.
Strong scripting skills using Perl/Tcl.
Strong written/verbal communication skills.
Minimum Qualifications
BS and a minimum of 2 years of relevant industry experience.
Pay & Benefits
At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $141,800 and $258,600, and your base pay will depend on your skills, qualifications, experience, and location.
Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
About Apple
Sourced by ZipRecruiter
Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it.
Industry
Computer and electronic product manufacturing
Company size
10,000+ Employees
Headquarters location
Cupertino, CA, US
Year founded
1976