Design Verification Engineer
$141K - $172K/yr
We have an opportunity for an outstandingly hardworking design verification engineer! As a member of our wide-ranging group, you will have the rare and extraordinary opportunity to craft upcoming ...
Design Verification Engineer
$141K - $172K/yr
We have an opportunity for an outstandingly hardworking design verification engineer! As a member of our wide-ranging group, you will have the rare and extraordinary opportunity to craft upcoming ...
Design Verification Engineer
Beaverton, OR · On-site
$141K - $172K/yr
Design Verification Engineers at Apple are responsible for verifying the functionality and performance of Apple's premier SOCs. This is a critical job within Apple's Hardware Technology and we'd love ...
Design Verification Engineer
Beaverton, OR · On-site
$141K - $172K/yr
Design Verification Engineers at Apple are responsible for verifying the functionality and performance of Apple's premier SOCs. This is a critical job within Apple's Hardware Technology and we'd love ...
Design Verification Engineer
$141K - $172K/yr
Design Verification Engineers at Apple are responsible for verifying the functionality and performance of Apple's premier SOCs. This is a critical job within Apple's Hardware Technology and we'd love ...
Design Verification Engineer
$141K - $172K/yr
Design Verification Engineers at Apple are responsible for verifying the functionality and performance of Apple's premier SOCs. This is a critical job within Apple's Hardware Technology and we'd love ...
Design Verification Engineer
Beaverton, OR · On-site
$141K - $172K/yr
We have an opportunity for an outstandingly hardworking design verification engineer! As a member of our wide-ranging group, you will have the rare and extraordinary opportunity to craft upcoming ...
Design Verification Engineer
Beaverton, OR · On-site
$141K - $172K/yr
We have an opportunity for an outstandingly hardworking design verification engineer! As a member of our wide-ranging group, you will have the rare and extraordinary opportunity to craft upcoming ...
SoC Physical Design Verification Engineer
$129K - $194K/yr
... engineering efforts. • You will work on padring, bump, RDL design, and working with the package and floorplan teams. Preferred Qualifications Experienced with physical verification flows such as ...
SoC Physical Design Verification Engineer
$129K - $194K/yr
... engineering efforts. • You will work on padring, bump, RDL design, and working with the package and floorplan teams. Preferred Qualifications Experienced with physical verification flows such as ...
SoC Physical Design Verification Engineer
$129K - $194K/yr
... engineering efforts. • You will work on padring, bump, RDL design, and working with the package and floorplan teams. Preferred Qualifications Experienced with physical verification flows such as ...
SoC Physical Design Verification Engineer
$129K - $194K/yr
... engineering efforts. • You will work on padring, bump, RDL design, and working with the package and floorplan teams. Preferred Qualifications Experienced with physical verification flows such as ...
Mixed Signal IP Verification Engineer
$122K - $232K/yr
Join Intel as a Mixed Signal Design Verification Engineer and play a crucial role in shaping the future of cutting-edge technology. In this role, you will be at the forefront of ensuring Intel ...
Mixed Signal IP Verification Engineer
$122K - $232K/yr
Join Intel as a Mixed Signal Design Verification Engineer and play a crucial role in shaping the future of cutting-edge technology. In this role, you will be at the forefront of ensuring Intel ...
Emulation Verification Engineer
$141K - $172K/yr
We are looking for you to join our design verification team focusing on the creation, deployment, and support of sophisticated emulation environments. In this highly transparent role, you will be at ...
Emulation Verification Engineer
$141K - $172K/yr
We are looking for you to join our design verification team focusing on the creation, deployment, and support of sophisticated emulation environments. In this highly transparent role, you will be at ...
Emulation Verification Engineer
Beaverton, OR · On-site
$141K - $172K/yr
We are looking for you to join our design verification team focusing on the creation, deployment, and support of sophisticated emulation environments. In this highly transparent role, you will be at ...
Emulation Verification Engineer
Beaverton, OR · On-site
$141K - $172K/yr
We are looking for you to join our design verification team focusing on the creation, deployment, and support of sophisticated emulation environments. In this highly transparent role, you will be at ...
As a logic design engineer, you will be involved in all phases of the design, from concept study, architecture definition, design and verification, to silicon bring-up and characterization.
As a logic design engineer, you will be involved in all phases of the design, from concept study, architecture definition, design and verification, to silicon bring-up and characterization.
DDR Design Engineer
Beaverton, OR · On-site
As a logic design engineer, you will be involved in all phases of the design, from concept study, architecture definition, design and verification, to silicon bring-up and characterization.
DDR Design Engineer
Beaverton, OR · On-site
As a logic design engineer, you will be involved in all phases of the design, from concept study, architecture definition, design and verification, to silicon bring-up and characterization.
RTL Design Engineer
Beaverton, OR · On-site
You will work to specify, design, verify, and support lab bring-up of sophisticated digital and ... Minimum Qualifications Bachelors of Science in Electrical Engineering. Preferred Qualifications ...
RTL Design Engineer
Beaverton, OR · On-site
You will work to specify, design, verify, and support lab bring-up of sophisticated digital and ... Minimum Qualifications Bachelors of Science in Electrical Engineering. Preferred Qualifications ...
ASIC Design Engineer
Beaverton, OR · On-site
We are searching for a dedicated engineer to join our exciting team of problem solvers. Description ... Verification, Emulation, STA, and Physical Design teams - Collaborate with software and systems ...
ASIC Design Engineer
Beaverton, OR · On-site
We are searching for a dedicated engineer to join our exciting team of problem solvers. Description ... Verification, Emulation, STA, and Physical Design teams - Collaborate with software and systems ...
We are searching for a dedicated engineer to join our exciting team of problem solvers. Description ... Verification, Emulation, STA, and Physical Design teams - Collaborate with software and systems ...
We are searching for a dedicated engineer to join our exciting team of problem solvers. Description ... Verification, Emulation, STA, and Physical Design teams - Collaborate with software and systems ...
Collaborate with cross-functional teams including RTL design, verification, and full-chip ... Collaborate with experienced engineers across architecture, design, and full-chip integration
Collaborate with cross-functional teams including RTL design, verification, and full-chip ... Collaborate with experienced engineers across architecture, design, and full-chip integration
Collaborate with cross-functional teams including RTL design, verification, and full-chip ... Collaborate with experienced engineers across architecture, design, and full-chip integration
Collaborate with cross-functional teams including RTL design, verification, and full-chip ... Collaborate with experienced engineers across architecture, design, and full-chip integration
Senior Engineer, Digital Design Engineering
Beaverton, OR · On-site
$121K - $174K/yr
Apply formal design and verification techniques to design and architect detailed verification plans ... Engineer or related occupation performing digital or mixed signal design and verification. Must ...
Senior Engineer, Digital Design Engineering
Beaverton, OR · On-site
$121K - $174K/yr
Apply formal design and verification techniques to design and architect detailed verification plans ... Engineer or related occupation performing digital or mixed signal design and verification. Must ...
Senior Engineer, Digital Design Engineering
Beaverton, OR · On-site
$121K - $174K/yr
Apply formal design and verification techniques to design and architect detailed verification plans ... Engineer or related occupation performing digital or mixed signal design and verification. Must ...
Senior Engineer, Digital Design Engineering
Beaverton, OR · On-site
$121K - $174K/yr
Apply formal design and verification techniques to design and architect detailed verification plans ... Engineer or related occupation performing digital or mixed signal design and verification. Must ...
You and your team will apply engineering fundamentals and start from scratch if needed, bringing ... verification and silicon bring up. - Work closely with layout team to complete the design and ...
You and your team will apply engineering fundamentals and start from scratch if needed, bringing ... verification and silicon bring up. - Work closely with layout team to complete the design and ...
Timing Design Engineer
Beaverton, OR · On-site
You will also come up with ideas and plans to verify your own timing constraints. You will innovate ... Engineering. Preferred Qualifications Proven knowledge of the ASIC design timing closure flow and ...
Timing Design Engineer
Beaverton, OR · On-site
You will also come up with ideas and plans to verify your own timing constraints. You will innovate ... Engineering. Preferred Qualifications Proven knowledge of the ASIC design timing closure flow and ...
Entry Level Design Verification Engineer information
See Oregon salary details
$111.5K - $117.5K
0% of jobs
$117.5K - $123.4K
0% of jobs
$123.4K - $129.3K
0% of jobs
$129.3K - $135.2K
0% of jobs
$135.2K - $141.1K
0% of jobs
$143.4K is the 25th percentile. Wages below this are outliers.
$141.1K - $147K
65% of jobs
$147K - $152.9K
0% of jobs
$152.9K - $158.8K
0% of jobs
$158.8K - $164.7K
0% of jobs
$164.7K - $170.7K
0% of jobs
$172.3K is the 75th percentile. Wages above this are outliers.
$170.7K - $176.6K
35% of jobs
$111.5K
$157.7K
$176.6K
How much do entry level design verification engineer jobs pay per year?
As of Jul 7, 2026, the average yearly pay for entry level design verification engineer in Oregon is $157,694.00, according to ZipRecruiter salary data. Most workers in this role earn between $143,800.00 and $175,500.00 per year, depending on experience, location, and employer.
What are the key skills and qualifications needed to thrive in the Entry Level Design Verification Engineer position, and why are they important?
To thrive as an Entry Level Design Verification Engineer, you need a solid understanding of digital logic design, computer architecture, and verification methodologies, typically supported by a degree in electrical engineering, computer engineering, or a related field. Familiarity with hardware description languages (such as Verilog or VHDL), simulation tools, and industry-standard verification frameworks is essential. Strong analytical skills, attention to detail, and effective communication are vital soft skills for diagnosing issues and collaborating with design teams. These skills ensure accurate verification of hardware designs and smooth integration within the broader engineering workflow.
What is an Entry Level Design Verification Engineer job?
An Entry Level Design Verification Engineer ensures that hardware designs function correctly before production. They write and run testbenches using languages like SystemVerilog and work with simulation tools to verify chip functionality. Their role involves debugging, analyzing test results, and collaborating with designers to refine designs. This position is crucial in the semiconductor industry to prevent costly design errors. Typically, they work with verification methodologies like UVM to create efficient and reusable test environments.
What are typical tasks and responsibilities for an Entry Level Design Verification Engineer on a daily basis?
As an Entry Level Design Verification Engineer, your daily activities often include writing and executing testbenches, analyzing simulation results, identifying design bugs, and collaborating closely with design and development engineers to resolve issues. You may also be responsible for maintaining verification documentation and participating in code reviews or team meetings. The role involves a mix of hands-on technical work and teamwork, allowing you to learn best practices from experienced colleagues. Over time, you'll have opportunities to take on more complex verification tasks and contribute to process improvements as you gain experience.
What are popular job titles related to Entry Level Design Verification Engineer jobs in Oregon? For Entry Level Design Verification Engineer jobs in Oregon, the most frequently searched job titles are:
What job categories do people searching Entry Level Design Verification Engineer jobs in Oregon look for? The top searched job categories for Entry Level Design Verification Engineer jobs in Oregon are:
What cities in Oregon are hiring for Entry Level Design Verification Engineer jobs? Cities in Oregon with the most Entry Level Design Verification Engineer job openings:
Apple rating
8.1
Based on 667 frontline employees who took The Breakroom Quiz
5th of 30 rated technology retailers
Job description
At Apple, we work every single day to craft products that enrich people’s lives. Do you love working on challenges that no one has solved yet and changing the game? We have an opportunity for an outstandingly hardworking design verification engineer! As a member of our wide-ranging group, you will have the rare and extraordinary opportunity to craft upcoming products that will delight and encourage millions of Apple’s customers daily.
This role is for a DV engineer who will enable us to produce fully functional first silicon for IP designs. The responsibilities include all phases of pre-silicon verification including but not limited to: establishing DV methodology, test-plan development, verification environment development including stimulus and checkers, test-writing, debug, coverage, sign-off for RTL freeze and tape-out.
Description
In this role, you will be responsible for ensuring bug-free first silicon for part of the SoC / IP and are encouraged to develop detailed test and coverage plans based on the micro-architecture You are responsible for developing verification methodology suitable for the IP, ensuring a scalable and portable environment. You will get to develop verification environment, including all the respective components such as stimulus, checkers, assertions, trackers, coverage. A mindset to break the design is highly desirable.
Furthermore, you will learn to develop verification plans for all features under your care, implement verification plans, including design bring-up, DV environment bring- up, regression enabling all features under your care, and debug of the test failures. You will also learn to develop block, IP and SoC level test-benches track and report DV progress using a variety of metrics, including bugs and coverage. You will also be expected to make use of LLM and related technologies to achieve efficient execution and improved quality.","responsibilities":"Study design specification and create test plan
Develop infrastructure in SystemVerilog/UVM to stress the design
Develop and fix failures from regressions, close bugs
Use LLMs to do verification efficiently
Preferred Qualifications
BS degree in technical subject area with minimum 3 years of proven experience or equivalent strongly preferred
Strong knowledge of OOP, SystemVerilog and UVM
Strong knowledge in developing scalable and portable test-benches
Proven experience with verification methodologies and tools such as simulators, waveform viewer, build and run automation, coverage collection, gate level simulations
Some working experience using LLMs for efficiency and quality
Experience with power-aware (UPF) or similar verification methodology
Knowledge of one of the scripting languages such as Python, Perl, TCL
Some experience with serial protocols such as PCIe or USB, parallel protocol such as DDR is a plus but not required
Knowledge of formal verification methodology is a plus but not required
Knowledge of emulation for verification technologies is a plus but not required
Minimum Qualifications
Minimum requirement of a bachelors degree
This role is for a DV engineer who will enable us to produce fully functional first silicon for IP designs. The responsibilities include all phases of pre-silicon verification including but not limited to: establishing DV methodology, test-plan development, verification environment development including stimulus and checkers, test-writing, debug, coverage, sign-off for RTL freeze and tape-out.
Description
In this role, you will be responsible for ensuring bug-free first silicon for part of the SoC / IP and are encouraged to develop detailed test and coverage plans based on the micro-architecture You are responsible for developing verification methodology suitable for the IP, ensuring a scalable and portable environment. You will get to develop verification environment, including all the respective components such as stimulus, checkers, assertions, trackers, coverage. A mindset to break the design is highly desirable.
Furthermore, you will learn to develop verification plans for all features under your care, implement verification plans, including design bring-up, DV environment bring- up, regression enabling all features under your care, and debug of the test failures. You will also learn to develop block, IP and SoC level test-benches track and report DV progress using a variety of metrics, including bugs and coverage. You will also be expected to make use of LLM and related technologies to achieve efficient execution and improved quality.","responsibilities":"Study design specification and create test plan
Develop infrastructure in SystemVerilog/UVM to stress the design
Develop and fix failures from regressions, close bugs
Use LLMs to do verification efficiently
Preferred Qualifications
BS degree in technical subject area with minimum 3 years of proven experience or equivalent strongly preferred
Strong knowledge of OOP, SystemVerilog and UVM
Strong knowledge in developing scalable and portable test-benches
Proven experience with verification methodologies and tools such as simulators, waveform viewer, build and run automation, coverage collection, gate level simulations
Some working experience using LLMs for efficiency and quality
Experience with power-aware (UPF) or similar verification methodology
Knowledge of one of the scripting languages such as Python, Perl, TCL
Some experience with serial protocols such as PCIe or USB, parallel protocol such as DDR is a plus but not required
Knowledge of formal verification methodology is a plus but not required
Knowledge of emulation for verification technologies is a plus but not required
Minimum Qualifications
Minimum requirement of a bachelors degree
About Apple
Sourced by ZipRecruiter
Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it.
Industry
Computer and electronic product manufacturing
Company size
10,000+ Employees
Headquarters location
Cupertino, CA, US
Year founded
1976