Sr. ASIC Design Engineer This role has been designed as ''Onsite' with an expectation that you will primarily work from an HPE office. Who We Are: Hewlett Packard Enterprise is the global edge-to ...
Sr. ASIC Design Engineer This role has been designed as ''Onsite' with an expectation that you will primarily work from an HPE office. Who We Are: Hewlett Packard Enterprise is the global edge-to ...
As a Pixel IP DMA Design Engineer in the Pixel IP team, you will work closely with architecture ... front-end ASIC RTL designTight-knit collaboration skills with excellent written and verbal ...
As a Pixel IP DMA Design Engineer in the Pixel IP team, you will work closely with architecture ... front-end ASIC RTL designTight-knit collaboration skills with excellent written and verbal ...
As a Senior ASIC Design Engineer, you will be part of an advanced design and architecture team that is creating the semiconductor designs which will power millions of new Amazon devices. You will ...
As a Senior ASIC Design Engineer, you will be part of an advanced design and architecture team that is creating the semiconductor designs which will power millions of new Amazon devices. You will ...
As a Senior ASIC Design Engineer, you will be part of an advanced design and architecture team that is creating the semiconductor designs which will power millions of new Amazon devices. You will ...
As a Senior ASIC Design Engineer, you will be part of an advanced design and architecture team that is creating the semiconductor designs which will power millions of new Amazon devices. You will ...
ASIC Design Engineer, Cloud-Scale Machine Learning Acceleration team - Annapurna Labs
Cupertino, CA · On-site
Key job responsibilities As an ASIC Design Engineer, you will: Develop and implement high-performance, area and power-efficient RTL designs to meet project specifications and targets Conduct in-depth ...
ASIC Design Engineer, Cloud-Scale Machine Learning Acceleration team - Annapurna Labs
Cupertino, CA · On-site
Key job responsibilities As an ASIC Design Engineer, you will: Develop and implement high-performance, area and power-efficient RTL designs to meet project specifications and targets Conduct in-depth ...
Analog/Mixed Signal ASIC Design Engineer
San Diego, CA · On-site
$115.60K - $173.40K/yr
Master's degree in Electrical Engineering or related field. * Demostrated interrest in analog circuit design by course selections and/or work experience. * Experience working with ASIC design tools ...
Analog/Mixed Signal ASIC Design Engineer
San Diego, CA · On-site
$115.60K - $173.40K/yr
Master's degree in Electrical Engineering or related field. * Demostrated interrest in analog circuit design by course selections and/or work experience. * Experience working with ASIC design tools ...
Key job responsibilities As an ASIC Design Engineer, you will: Develop and implement high-performance, area and power-efficient RTL designs to meet project specifications and targets Conduct in-depth ...
Key job responsibilities As an ASIC Design Engineer, you will: Develop and implement high-performance, area and power-efficient RTL designs to meet project specifications and targets Conduct in-depth ...
Come work at Amazon! We're hiring an ASIC Engineer within a high performance ASIC design team. This team is using industry leading methodologies to develop proprietary IP's. The Role: Be part of Leo ...
Come work at Amazon! We're hiring an ASIC Engineer within a high performance ASIC design team. This team is using industry leading methodologies to develop proprietary IP's. The Role: Be part of Leo ...
We are now looking for an ASIC Design Efficiency Engineer! NVIDIA is seeking extraordinary methodology engineers to design hardware accelerators and processors on our next-generation mobile, embedded ...
We are now looking for an ASIC Design Efficiency Engineer! NVIDIA is seeking extraordinary methodology engineers to design hardware accelerators and processors on our next-generation mobile, embedded ...
Principal ASIC Test Development Engineer This role has been designed as 'Hybrid' with an ... Works closely with design teams to enable the DFT features in ASICs, validate on ATE, integrate in ...
Principal ASIC Test Development Engineer This role has been designed as 'Hybrid' with an ... Works closely with design teams to enable the DFT features in ASICs, validate on ATE, integrate in ...
Principal ASIC Test Development Engineer This role has been designed as 'Hybrid' with an ... Works closely with design teams to enable the DFT features in ASICs, validate on ATE, integrate in ...
Principal ASIC Test Development Engineer This role has been designed as 'Hybrid' with an ... Works closely with design teams to enable the DFT features in ASICs, validate on ATE, integrate in ...
Principal ASIC Test Development Engineer This role has been designed as 'Hybrid' with an ... Works closely with design teams to enable the DFT features in ASICs, validate on ATE, integrate in ...
Principal ASIC Test Development Engineer This role has been designed as 'Hybrid' with an ... Works closely with design teams to enable the DFT features in ASICs, validate on ATE, integrate in ...
Engineer I-Design (ASIC)
San Jose, CA · On-site
Master's in Electrical Engineering, Computer Engineering or Computer Science. * FPGA and ASIC System On Chip Design Experience. * Lab Experience for system-level validation. Travel Time: 0% - 25 ...
Engineer I-Design (ASIC)
San Jose, CA · On-site
Master's in Electrical Engineering, Computer Engineering or Computer Science. * FPGA and ASIC System On Chip Design Experience. * Lab Experience for system-level validation. Travel Time: 0% - 25 ...
Principal ASIC Test Development Engineer This role has been designed as 'Hybrid' with an ... Works closely with design teams to enable the DFT features in ASICs, validate on ATE, integrate in ...
Principal ASIC Test Development Engineer This role has been designed as 'Hybrid' with an ... Works closely with design teams to enable the DFT features in ASICs, validate on ATE, integrate in ...
Principal ASIC Test Development Engineer This role has been designed as 'Hybrid' with an ... Works closely with design teams to enable the DFT features in ASICs, validate on ATE, integrate in ...
Principal ASIC Test Development Engineer This role has been designed as 'Hybrid' with an ... Works closely with design teams to enable the DFT features in ASICs, validate on ATE, integrate in ...
Principal ASIC Test Development Engineer This role has been designed as 'Hybrid' with an ... Works closely with design teams to enable the DFT features in ASICs, validate on ATE, integrate in ...
Principal ASIC Test Development Engineer This role has been designed as 'Hybrid' with an ... Works closely with design teams to enable the DFT features in ASICs, validate on ATE, integrate in ...
We are now looking for an ASIC Design Efficiency Engineer! NVIDIA is seeking extraordinary methodology engineers to design hardware accelerators and processors on our next-generation mobile, embedded ...
We are now looking for an ASIC Design Efficiency Engineer! NVIDIA is seeking extraordinary methodology engineers to design hardware accelerators and processors on our next-generation mobile, embedded ...
Principal ASIC Test Development Engineer This role has been designed as 'Hybrid' with an ... Works closely with design teams to enable the DFT features in ASICs, validate on ATE, integrate in ...
Principal ASIC Test Development Engineer This role has been designed as 'Hybrid' with an ... Works closely with design teams to enable the DFT features in ASICs, validate on ATE, integrate in ...
We are now looking for an ASIC Design Efficiency Engineer! NVIDIA is seeking extraordinary methodology engineers to design hardware accelerators and processors on our next-generation mobile, embedded ...
We are now looking for an ASIC Design Efficiency Engineer! NVIDIA is seeking extraordinary methodology engineers to design hardware accelerators and processors on our next-generation mobile, embedded ...
Engineer I-Design (ASIC)
San Jose, CA · On-site
Master's in Electrical Engineering, Computer Engineering or Computer Science. * FPGA and ASIC System On Chip Design Experience. * Lab Experience for system-level validation. Travel Time: 0% - 25 ...
Engineer I-Design (ASIC)
San Jose, CA · On-site
Master's in Electrical Engineering, Computer Engineering or Computer Science. * FPGA and ASIC System On Chip Design Experience. * Lab Experience for system-level validation. Travel Time: 0% - 25 ...
Entry Level Asic Design Engineer information
See salary details
$94K - $103.8K
16% of jobs
$103.8K - $113.6K
3% of jobs
$113.6K - $123.5K
4% of jobs
$126.3K is the 25th percentile. Wages below this are outliers.
$123.5K - $133.3K
6% of jobs
The median wage is $139.4K / yr.
$133.3K - $143.1K
33% of jobs
$143.1K - $152.9K
3% of jobs
$152.9K - $162.7K
2% of jobs
$169.2K is the 75th percentile. Wages above this are outliers.
$162.7K - $172.5K
12% of jobs
$172.5K - $182.4K
5% of jobs
$182.4K - $192.2K
4% of jobs
$192.2K - $202K
12% of jobs
$94K
$150.2K
$202K
How much do entry level asic design engineer jobs pay per year?
What is an Entry Level ASIC Design Engineer job?
What are the key skills and qualifications needed to thrive in the Entry Level Asic Design Engineer position, and why are they important?
What are the typical daily responsibilities for an Entry Level ASIC Design Engineer?
- What are the key skills and qualifications needed to thrive in the Entry Level Asic Design Engineer position and why are they important?
- What are the typical daily responsibilities for an Entry Level ASIC Design Engineer?
- What is an Entry Level ASIC Design Engineer job?
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Hewlett Packard Enterprise rating
8.3
Based on 23 frontline employees who took The Breakroom Quiz
30th of 137 rated electronics manufacturers
Job description
Who We Are:
Hewlett Packard Enterprise is the global edge-to-cloud company advancing the way people live and work. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today's complex world.Our culture thrives onfinding new and better ways to accelerate what's next.We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs.We make bold moves, together, and are a force for good. If you are looking to stretch and grow your career our culture will embrace you.Open up opportunities with HPE.
Job Description:
Job Family Definition:
HPE Networking is a leading provider of advanced routers and switches for the internet.We keep the world connected with speed, reliability, security, and ease of use.At HPE Networking Silicon group, we push the boundaries of what is possible in a piece of silicondie.We buildcutting edgenetworking chips used to buildourworld-class routers and switches.
Bring your passion and there are no boundaries to what you canaccomplishhere. We are likea start-up in a big company. Year after year, our group builds the most powerful and highest density networking chips.
As part of our fast-pacedsilicongroup, you willbecome an expertinbuildinghigh-speedASICs, from specifications to final netlist.We give you opportunities to work on complexmodules and subsystemswhere you can challenge yourself and grow.
Open communications, empowerment, innovation,teamwork,and customer success are the foundations ofteamculture.Thus, you set your own limits for learning,achievements,and rewards.
Responsibilities:
You will start with a functional specification of a module and produce a detailed micro-architecturespecificationthat meets the power/area requirements.
You will implement the design using Verilog or System Verilog
Write functional coverage/SVAto help verification catch corner casebugs.
You will work withthe PhysicalDesign team foroptimalfloorplan andtiming closure. You willidentifyand fix timing in RTL to meet the frequency target.
Work with the Verification team to make sure your block is fullyvalidated.
You will have opportunities to improveleadershipskillsby providingmentoring/guidance to new college-grad engineers andinterns.
Recommended skills
Bachelor's degree in Electrical Engineeringrequired(Master'sstronglydesired) with 5+years of relevantexperience.
Strong analytical/problem solving skills.
Knowledge of Computer Architecture/networking protocols through graduate level courses orpriorworkis a plus.
Strong coding skills in Verilog/System Verilog through courses/projects andpreviouswork experienceisdesired.
Knowledge of synthesis/lintand otherstate-of-the-artEDA toolsisdesired.
Excellent written and verbalcommunicationsskillsaregood to have.
Knowledge of Perl/Python is aplus.
Experience with AI agentic tools is a plus.
What We Can Offer You:
Health & Wellbeing
We strive to provide our team members and their loved ones with a comprehensive suite of benefits that supports their physical, financial and emotional wellbeing.
Personal & Professional Development
We also invest in your career because the better you are, the better we all are. We have specific programs catered to helping you reach any career goals you have - whether you want to become a knowledge expert in your field or apply your skills to another division.
Unconditional Inclusion
We are unconditionally inclusive in the way we work and celebrate individual uniqueness. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good.
Let's Stay Connected:
Follow @HPECareers on Instagram to see the latest on people, culture and tech at HPE.
Job:
EngineeringJob Level:
TCP_04"The expected salary/wage range for this position is provided below. Actual offer may vary from this range based upon geographic location, work experience, education/training, and/or skill level.- United States of America: Annual Salary USD 153,500 - 310,500 in California
The listed salary range reflects base salary. Variable incentives may also be offered."
Information about employee benefits offered in the US can be found at https://myhperewards.com/main/new-hire-enrollment.html
HPE is an Equal Employment Opportunity/ Veterans/Disabled/LGBT employer. We do not discriminate on the basis of race, gender, or any other protected category, and all decisions we make are made on the basis of qualifications, merit, and business need. Our goal is to be one global team that is representative of our customers, in an inclusive environment where we can continue to innovate and grow together. Please click here: Equal Employment Opportunity.
Hewlett Packard Enterprise is EEO Protected Veteran/ Individual with Disabilities.
HPE will comply with all applicable laws related to employer use of arrest and conviction records, including laws requiring employers to consider for employment qualified applicants with criminal histories.
No Fees Notice & Recruitment Fraud Disclaimer
It has come to HPE's attention that there has been an increase in recruitment fraud whereby scammer impersonate HPE or HPE-authorized recruiting agencies and offer fake employment opportunities to candidates. These scammers often seek to obtain personal information or money from candidates.
Please note that Hewlett Packard Enterprise (HPE), its direct and indirect subsidiaries and affiliated companies, and its authorized recruitment agencies/vendorswill never charge any candidate a registration fee, hiring fee, or any other fee in connection with its recruitment and hiring process.The credentials of any hiring agency that claims to be working with HPE for recruitment of talent should be verified by candidates and candidates shall be solely responsible to conduct such verification. Any candidate/individual who relies on the erroneous representations made by fraudulent employment agencies does so at their own risk, and HPE disclaims liability for any damages or claims that may result from any such communication.
What Hewlett Packard Enterprise employees say
Pay
Hours and flexibility
Workplace
Get the full story on Breakroom
About Hewlett Packard Enterprise
Sourced by ZipRecruiter
Industry
It services
Company size
10,000+ Employees
Headquarters location
Spring, TX, US
Year founded
2015