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Chip Design Jobs in Seattle, WA (NOW HIRING)

K2 Space

Senior ASIC Physical Design Engineer

Seattle, WA · On-site

$170K - $250K/yr

Experience with chip-package co-design or advanced packaging (2.5D/3D). * Familiarity with physical ... design service vendor management or offshore collaboration. * Experience with sign-off through TSMC.

Nvidia

Senior Digital Design Engineer

Redmond, WA · On-site

Collaborate with chip architects, verification engineers, formal verification engineers, and SoC ... Deep understanding of ASIC design flows and methodology * Strong analytical and interpersonal ...

Nvidia

Senior Digital Design Engineer

Redmond, WA

Collaborate with chip architects, verification engineers, formal verification engineers, and SoC ... Deep understanding of ASIC design flows and methodology Strong analytical and interpersonal skills ...

Nvidia

Senior GPU Memory Architect

Seattle, WA

An understanding in CPU or GPU architecture, memory systems, or network on-chip design. Experience in large-scale SW development projects and strong programming skills in C/C++ and Python or other ...

ARM

Graduate Program - Engineering Pathways

Seattle, WA · On-site

$119K - $161K/yr

Hardware & Chip Design -- Design Arm technology through digital logic, RTL, FPGA, circuits, physical design or semiconductor technology. Testing & Validation -- Test and debug technology before and ...

Nvidia

Senior GPU Memory Architect

Seattle, WA · On-site

An understanding in CPU or GPU architecture, memory systems, or network on-chip design. * Experience in large-scale SW development projects and strong programming skills in C/C++ and Python or other ...

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Showing results 21-40

All JobsChip Design JobsChip Design Jobs in Seattle, WA

Chip Design information

See Seattle, WA salary details

$47.8K

$130.3K

$229.3K

How much do chip design jobs pay per year?

As of Sep 7, 2026, the average yearly pay for chip design in Seattle, WA is $130,294.00, according to ZipRecruiter salary data. Most workers in this role earn between $95,000.00 and $163,900.00 per year, depending on experience, location, and employer.

What is a chip design?

A Chip Design job involves creating and developing semiconductor circuits used in electronic devices. Engineers in this field work on designing, verifying, and testing integrated circuits (ICs) to ensure performance, power efficiency, and reliability. They use specialized software tools for designing hardware and optimizing functionality. Chip designers collaborate with cross-functional teams to bring new processors, memory chips, or custom ASICs from concept to production. This role is crucial in industries like computing, telecommunications, and consumer electronics.

What are the key skills and qualifications needed to thrive in chip design?

To excel in Chip Design, a strong background in electrical engineering, digital and analog circuit design, and semiconductor physics is typically required, often supported by a relevant engineering degree. Familiarity with electronic design automation (EDA) tools like Cadence, Synopsys, and Mentor Graphics, as well as proficiency in hardware description languages (HDLs) such as Verilog or VHDL, are standard prerequisites. Outstanding problem-solving skills, attention to detail, and the ability to collaborate closely with cross-functional teams set candidates apart. These competencies are essential for designing efficient, reliable integrated circuits and meeting the evolving needs of the semiconductor industry.

What are the typical career progression opportunities in chip design?

Chip Design offers a clear pathway for career growth, starting from entry-level positions such as Design Engineer or Verification Engineer and progressing to roles like Lead Designer, Project Manager, or Technical Architect. As you gain experience and demonstrate expertise, opportunities often open up in specialized areas such as physical design, timing analysis, or system architecture. Many professionals also advance to leadership or managerial positions, overseeing teams or entire design projects. Additionally, working in such a fast-evolving field keeps you engaged with the latest technologies and can provide options to transition into adjacent areas like product management or application engineering.

How much do chip designers make?

Chip designers, also known as integrated circuit designers, typically earn between $80,000 and $150,000 annually, depending on experience, education, and location. Senior roles or those with specialized skills in hardware description languages and CAD tools can earn higher salaries, often exceeding $200,000.

How to get a job in chip design?

To get a job in chip design, candidates typically need a bachelor's degree in electrical engineering, computer engineering, or a related field, along with strong skills in digital and analog circuit design, hardware description languages like VHDL or Verilog, and familiarity with CAD tools. Gaining experience through internships, projects, or research can improve employability, and advanced roles may require a master's or Ph.D. in a relevant area. Certifications in specific design tools or methodologies can also enhance prospects.

Is chip design a good career?

Chip design is a specialized field within electrical engineering focused on developing integrated circuits and microprocessors. It offers high demand, competitive salaries, and opportunities for innovation, often requiring skills in hardware description languages and familiarity with CAD tools. Career growth depends on technical expertise and industry experience.

What are the most commonly searched types of Chip Design jobs in Seattle, WA?

The most popular types of Chip Design jobs in Seattle, WA are:

What are popular job titles related to Chip Design jobs in Seattle, WA?

For Chip Design jobs in Seattle, WA, the most frequently searched job titles are:

What job categories do people searching Chip Design jobs in Seattle, WA look for?

The top searched job categories for Chip Design jobs in Seattle, WA are:

Chip Design jobs near you
Infographic showing various Chip Design job openings in Seattle, WA as of August 2026, with employment types broken down into 100% Full Time. Highlights an 89% In-person, and 11% Hybrid job distribution, with an average salary of $130,294 per year, or $62.6 per hour.

Principal ASIC Physical Design Engineer

K2 Space

Seattle, WA

$190K - $280K/yr

Full-time

Medical, Dental, Vision, Life, PTO

Re-posted 8 days ago

Job description

K2 is building the largest and highest-power satellites ever flown, unlocking performance levels previously out of reach across every orbit. Backed by over $1 billion in total funding from leading investors including Altimeter Capital, ICONIQ, Kleiner Perkins, Lightspeed Venture Partners, Redpoint Ventures, and T. Rowe Price — and with over $1 billion in signed contracts across commercial and US government customers, we're mass-producing the highest-power satellite platforms ever built for missions from LEO to deep space.

The rise of heavy-lift launch vehicles is shifting the industry from an era of mass constraint to one of mass abundance, and we believe this new era demands a fundamentally different class of spacecraft. Engineered to survive the harshest radiation environments and to fully capitalize on today's and tomorrow's massive rockets, K2 satellites deliver unmatched capability at constellation scale and across multiple orbits.

With multiple launches in 2027 and plans to scale to 100 satellites a year, we're Building Bigger — helping develop the solar system and build toward a Kardashev Type II (K2) civilization. If you are a motivated individual who thrives in a fast-paced environment and you're excited about contributing to the success of a high-growth Series D-funded company, we'd love for you to apply.

The Role

We are looking for a Principal ASIC Physical Design Engineer to lead the implementation of complex SoCs for next-generation satellite and space systems. You will own the full physical design flow—from RTL handoff to GDSII—and collaborate closely with architecture, RTL design, DFT, and packaging teams. This role also involves managing external physical design partners, driving tool and flow decisions, and ensuring first-pass silicon success in advanced FinFET technologies. You'll be a key contributor in achieving timing closure, optimizing PPA, and supporting design integration with external partners. You will be part of a collaborative design team developing state-of-the-art mixed-signal SoCs to be hosted on some of the largest, most powerful, rapidly designed and rapidly manufactured satellites ever deployed in space. In your first 6 months, you will develop and implement new SoC sub-systems for satellite communications and beyond. In your first two years, you will have contributed to developing cutting-edge SoCs that will fly in space. 

Responsibilities

  • Own the complete RTL-to-GDSII flow: synthesis, floorplanning, place & route, clock tree synthesis (CTS), static timing analysis (STA), physical verification (DRC/LVS), and sign-off.
  • Develop and maintain physical design methodologies, scripts, and automation to optimize performance, power, and area (PPA).
  • Collaborate with front-end and verification teams to ensure clean handoffs, timing closure, and efficient design iteration.
  • Drive timing closure across multiple voltage and process corners, including sign-off with foundry-qualified tools.
  • Partner with package, SI/PI, and test teams for package-aware floorplanning and chip-to-board integration.
  • Manage and technically guide external physical design partners and service vendors, ensuring alignment on milestones, deliverables, and quality standards.
  • Work with EDA vendors to debug and optimize tool flows, and evaluate new methodologies.
  • Support chip bring-up and debug through close collaboration with post-silicon and test teams.
  • Support your product through production and spaceflight.

Required Qualifications 

  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.
  • 10+ years of experience in ASIC physical design for high-performance SoCs.
  • Proven end-to-end expertise in RTL-to-GDSII flows using industry tools (Synopsys, Cadence, or Siemens).
  • Strong hands-on experience with timing closure, IR drop analysis, and ECO implementation.
  • Deep understanding of physical design constraints for multi-clock, multi-voltage, and hierarchical SoCs.
  • Experience with advanced FinFET process nodes.
  • Prior experience managing or coordinating offshore/outsourced PD teams or vendors.
  • Familiarity with DFT integration, STA sign-off, and power domain implementation (UPF/CPF).
  • Excellent communication, leadership, and cross-functional collaboration skills.
  • Act as technical leader and subject-matter expert helping to teach, grow, and mentor others in the team.

Preferred Qualifications 

  • Exposure to radiation-hardened or space-qualified ASICs.
  • Experience with chip-package co-design or advanced packaging (2.5D/3D).
  • Familiarity with physical design service vendor management or offshore collaboration.
  • Experience driving tapeouts through TSMC.
  • Experience with Gate-All-Around technologies.
  • Experience working in cross-functional, geographically distributed teams.

Compensation and Benefits:

  • Base salary range for this role is $190,000 – $280,000 + equity in the company
  • Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
  • Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks

If you don't meet 100% of the preferred skills and experience, we encourage you to still apply! Building a spacecraft unlike any other requires a team unlike any other and non-traditional career twists and turns are encouraged!

If you need a reasonable accommodation as part of your application for employment or interviews with us, please let us know.

Export Compliance

As defined in the ITAR, "U.S. Persons" include U.S. citizens, lawful permanent residents (i.e., Green Card holders), and certain protected individuals (e.g., refugees/asylees, American Samoans). Please consult with a knowledgeable advisor if you are unsure whether you are a "U.S. Person."

The person hired for this role will have access to information and items controlled by U.S. export control regulations, including the export control regulations outlined in the International Traffic in Arms Regulation (ITAR). The person hired for this role must therefore either be a "U.S. person" as defined by 22 C.F.R. § 120.15 or otherwise eligible for a federally issued export control license.

Equal Opportunity

K2 Space is an Equal Opportunity Employer; employment with K2 Space is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.

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About K2 Space

Sourced by ZipRecruiter

Industry

Guided missile and space vehicle manufacturing

Company size

11 - 50 Employees

Headquarters location

Los Angeles, CA, US

Year founded

2022

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