Chandler, AZ · On-site
$101K - $136K/yr
Strong digital design engineer with FPGA/ASIC SoC design experience * Strong FPGA Implementation ... Proficient in SW development with C, C++ and GIT version control * Proficient in Microsoft Office ...
Chandler, AZ · On-site
$101K - $136K/yr
Strong digital design engineer with FPGA/ASIC SoC design experience * Strong FPGA Implementation ... Proficient in SW development with C, C++ and GIT version control * Proficient in Microsoft Office ...
Chandler, AZ · On-site
$101K - $136K/yr
Strong digital design engineer with FPGA/ASIC SoC design experience * Strong FPGA Implementation ... Proficient in SW development with C, C++ and GIT version control * Proficient in Microsoft Office ...
Quick apply
Chandler, AZ · On-site
$101K - $136K/yr
Strong digital design engineer with FPGA/ASIC SoC design experience * Strong FPGA Implementation ... Proficient in SW development with C, C++ and GIT version control * Proficient in Microsoft Office ...
Phoenix, AZ · On-site
$150 - $200/hr
Architect FPGA-, ASIC-, and processor-based digital hardware for high-reliability systems.* Lead ... Experience with FPGA development, simulation, verification, or timing analysis tools.* Experience ...
Phoenix, AZ · On-site
$150 - $200/hr
Architect FPGA-, ASIC-, and processor-based digital hardware for high-reliability systems.* Lead ... Experience with FPGA development, simulation, verification, or timing analysis tools.* Experience ...
Phoenix, AZ · On-site
$185K - $202K/yr
Architect FPGA-, ASIC-, and processor-based digital hardware for high-reliability systems. * Lead ... Experience with FPGA development, simulation, verification, or timing analysis tools. * Experience ...
Phoenix, AZ · On-site
$185K - $202K/yr
Architect FPGA-, ASIC-, and processor-based digital hardware for high-reliability systems. * Lead ... Experience with FPGA development, simulation, verification, or timing analysis tools. * Experience ...
Phoenix, AZ · On-site
$185K - $202K/yr
Architect FPGA-, ASIC-, and processor-based digital hardware for high-reliability systems. * Lead ... Experience with FPGA development, simulation, verification, or timing analysis tools. * Experience ...
Phoenix, AZ · On-site
$185K - $202K/yr
Architect FPGA-, ASIC-, and processor-based digital hardware for high-reliability systems. * Lead ... Experience with FPGA development, simulation, verification, or timing analysis tools. * Experience ...
Tucson, AZ · On-site
$128K - $156K/yr
Test case development will include the use of directed random test generators, device driver and ... Responsible for all test software required to verify a SOC ASIC. * May include integrating new ...
Tucson, AZ · On-site
$128K - $156K/yr
Test case development will include the use of directed random test generators, device driver and ... Responsible for all test software required to verify a SOC ASIC. * May include integrating new ...
Phoenix, AZ · Hybrid
$173K - $330K/yr
... ASIC tools/flows and Physical verification/runsets, Tape-in Verification and IP sign off for test ... Promote team values, accountability, and continuous improvement while guiding employee development ...
Phoenix, AZ · Hybrid
$173K - $330K/yr
... ASIC tools/flows and Physical verification/runsets, Tape-in Verification and IP sign off for test ... Promote team values, accountability, and continuous improvement while guiding employee development ...
Development engineers participate in various aspects of the development, test, and support process ... Microprocessor/ASIC Design Skills: VHDL, Verilog, RTL, SPICE, TCL, UVM, verification, and testing
Development engineers participate in various aspects of the development, test, and support process ... Microprocessor/ASIC Design Skills: VHDL, Verilog, RTL, SPICE, TCL, UVM, verification, and testing
Tucson, AZ · On-site
$80 - $100/hr
Development engineers participate in various aspects of the development, test, and support process ... Microprocessor/ASIC Design Skills: VHDL, Verilog, RTL, SPICE, TCL, UVM, verification, and testing
Tucson, AZ · On-site
$80 - $100/hr
Development engineers participate in various aspects of the development, test, and support process ... Microprocessor/ASIC Design Skills: VHDL, Verilog, RTL, SPICE, TCL, UVM, verification, and testing
Collaborate heavily with ASIC design, logic design (RTL), and verification teams to define hardware ... level silicon firmware development. Technical Skill Set * Language Masteries: Expert-level ...
Quick apply
Collaborate heavily with ASIC design, logic design (RTL), and verification teams to define hardware ... level silicon firmware development. Technical Skill Set * Language Masteries: Expert-level ...
Collaborate heavily with ASIC design, logic design (RTL), and verification teams to define hardware ... level silicon firmware development. Technical Skill Set * Language Masteries: Expert-level ...
Collaborate heavily with ASIC design, logic design (RTL), and verification teams to define hardware ... level silicon firmware development. Technical Skill Set * Language Masteries: Expert-level ...
Tucson, AZ · On-site
$98K - $132K/yr
We engage at the outset of the weapon system development and follow our designs through deployment ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
Tucson, AZ · On-site
$98K - $132K/yr
We engage at the outset of the weapon system development and follow our designs through deployment ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
We engage at the outset of the weapon system development and follow our designs through deployment ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
We engage at the outset of the weapon system development and follow our designs through deployment ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
Tucson, AZ · On-site
$98K - $132K/yr
We engage at the outset of the weapon system development and follow our designs through deployment ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
Tucson, AZ · On-site
$98K - $132K/yr
We engage at the outset of the weapon system development and follow our designs through deployment ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
Tucson, AZ · On-site
$98K - $132K/yr
We engage at the outset of the weapon system development and follow our designs through deployment ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
Tucson, AZ · On-site
$98K - $132K/yr
We engage at the outset of the weapon system development and follow our designs through deployment ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
Tucson, AZ · On-site
$96K - $130K/yr
We engage at the outset of the weapon system development and follow our designs through deployment ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
Tucson, AZ · On-site
$96K - $130K/yr
We engage at the outset of the weapon system development and follow our designs through deployment ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
... Support package floorplan development considering die placement, bump maps, power/ground ... ASIC physical design teams to help co-optimize the die-package interface. - Contribute to cross ...
... Support package floorplan development considering die placement, bump maps, power/ground ... ASIC physical design teams to help co-optimize the die-package interface. - Contribute to cross ...
... Support package floorplan development considering die placement, bump maps, power/ground ... ASIC physical design teams to help co-optimize the die-package interface. - Contribute to cross ...
... Support package floorplan development considering die placement, bump maps, power/ground ... ASIC physical design teams to help co-optimize the die-package interface. - Contribute to cross ...
... Support package floorplan development considering die placement, bump maps, power/ground ... ASIC physical design teams to help co-optimize the die-package interface. - Contribute to cross ...
... Support package floorplan development considering die placement, bump maps, power/ground ... ASIC physical design teams to help co-optimize the die-package interface. - Contribute to cross ...
... Support package floorplan development considering die placement, bump maps, power/ground ... ASIC physical design teams to help co-optimize the die-package interface. - Contribute to cross ...
... Support package floorplan development considering die placement, bump maps, power/ground ... ASIC physical design teams to help co-optimize the die-package interface. - Contribute to cross ...
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Job Title: Senior FPGA Engineer III
Department: Engineering->Platforms->FPGA SoC Group
Reports To: Director, Platforms
FLSA Status: Exempt
Last Modified: 9/10/2025
Level: T3
Location Chandler, AZ – Onsite 5 Days a week
Company Overview
Comtech Telecommunications Corp. is a leading global technology company providing terrestrial and wireless network solutions, next-generation 9-1-1 emergency services, satellite and space communications technologies, and cloud-native capabilities to commercial and government customers around the world. Our unique culture of innovation and employee empowerment unleashes a relentless passion for customer success. With multiple facilities located in technology corridors throughout the United States and around the world, Comtech leverages our global presence, technology leadership, and decades of experience to create the world’s most innovative communications solutions. For more information, please visit www.comtech.com.
We’re seeking curious, growth-minded thinkers to help shape our vision, structures, and systems; playing a key role as we launch into our ambitious future. If you’re invigorated by our mission, values, and drive to change the world — we’d love to have you apply.
Position Summary
Senior FPGA Designer with experience in the entire design flow for complex FPGA’s.
Responsibilities
Qualifications
Desired Qualifications
Education
Experience:
Comtech Telecommunications Corp. is an Equal Opportunity Employer. Qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, disability protected veteran status or other characteristics protected by law.
