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Asic Development Engineer Jobs in Tucson, AZ (NOW HIRING)

FPGA Engineer

Tucson, AZ

$122.90K - $157.90K/yr

... and perform code development, simulation, andplace and route. Designs are verified against ... FPGA/ASIC design (VHDL coding) or FPGA/ASIC verification (SystemVerilog coding with UVM) Xilinx or ...

FPGA Engineer

Tucson, AZ ยท On-site

$125.40K - $161.10K/yr

... perform code development, simulation, and place and route. Designs are verified against ... FPGA/ASIC design (VHDL coding) or FPGA/ASIC verification (SystemVerilog coding with UVM) * Xilinx ...

FPGA Engineer

Tucson, AZ ยท On-site

$125.40K - $161.10K/yr

... and perform code development, simulation, andplace and route. Designs are verified against ... to include the following: โ€ข FPGA/ASIC design (VHDL coding) or FPGA/ASIC verification ...

FPGA Engineer

Tucson, AZ ยท On-site

$122.90K - $157.90K/yr

... and perform code development, simulation, andplace and route. Designs are verified against ... to include the following: โ€ข FPGA/ASIC design (VHDL coding) or FPGA/ASIC verification ...

Senior FPGA Design Engineer

Tucson, AZ

$116.30K - $160.30K/yr

... development, we offer capabilities and opportunity no one else can. Together, we push the ... FPGA/ASIC design, including VHDL and/or Verilog coding or FPGA/ASIC verification using ...

Senior FPGA Design Engineer

Tucson, AZ ยท On-site

$116.30K - $160.30K/yr

... development, we offer capabilities and opportunity no one else can. Together, we push the ... FPGA/ASIC design, including VHDL and/or Verilog coding or FPGA/ASIC verification using ...

Senior FPGA Design Engineer

Tucson, AZ ยท On-site

$116.30K - $160.30K/yr

... development, we offer capabilities and opportunity no one else can. Together, we push the ... FPGA/ASIC design, including VHDL and/or Verilog coding or FPGA/ASIC verification using ...

FPGA Engineer

Tucson, AZ ยท On-site

$90/hr

... development or verification experience to join our team. What you will do Design and deliver ... FPGA/ASIC design (VHDL coding) or FPGA/ASIC verification (System Verilog coding with UVM) Xilinx or ...

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Asic Development Engineer information

See Tucson, AZ salary details

$46.3K

$90.9K

$145.1K

How much do asic development engineer jobs pay per year?

As of May 28, 2026, the average yearly pay for asic development engineer in Tucson, AZ is $90,912.00, according to ZipRecruiter salary data. Most workers in this role earn between $75,200.00 and $100,700.00 per year, depending on experience, location, and employer.

What is the difference between Asic Development Engineer vs FPGA Design Engineer?

AspectAsic Development EngineerFPGA Design Engineer
Required CredentialsBachelor's or Master's in Electrical Engineering, VLSI, or related fields; knowledge of ASIC design toolsBachelor's or Master's in Electrical Engineering, Digital Design; familiarity with FPGA development tools
Work EnvironmentDesigning and verifying custom silicon chips in semiconductor labs or R&D centersDeveloping and testing FPGA-based solutions in hardware labs or embedded systems environments
Industry UsageUsed in semiconductor companies, integrated circuit design firms, and tech giantsCommon in telecommunications, aerospace, and embedded systems industries

While both roles involve digital hardware design, Asic Development Engineers focus on creating custom chips for high-performance applications, whereas FPGA Design Engineers work on programmable hardware solutions. Both require strong digital design skills and familiarity with hardware description languages, but their end products and development environments differ.

What are popular job titles related to Asic Development Engineer jobs in Tucson, AZ? For Asic Development Engineer jobs in Tucson, AZ, the most frequently searched job titles are:
What job categories do people searching Asic Development Engineer jobs in Tucson, AZ look for? The top searched job categories for Asic Development Engineer jobs in Tucson, AZ are:
Infographic showing various Asic Development Engineer job openings in Tucson, AZ as of May 2026, with employment types broken down into 1% Internship, 10% Full Time, 78% Part Time, 1% Temporary, and 10% Contract. Highlights an 97% Physical, 1% Hybrid, and 2% Remote job distribution, with an average salary of $90,912 per year, or $43.7 per hour.

FPGA VHDL Design Engineer US Citizenship required

Science Referral Network

Tucson, AZ โ€ข On-site

$116.30K - $160.30K/yr

Full-time

Posted 23 days ago


Job description

Company Description
About Science Referral Network
We maintain a global network of well connected professionals in science, technology, engineering, and mathematics who are interested in working with us to help organizations recruit and hire the right technical talent for even the most specialized of tasks. Our network consists of both subject matter experts in a wide variety of technical areas and senior leaders at some of the world's most innovative, cutting edge organizations. We employ a system of strategic research and confidential targeted crowdsourcing throughout this network to help our clients identify and hire the talent they need.
Much more than just a database, we are continually working to strengthen all of the individual connections that make up our network. We strive to develop mutually beneficial, trusting relationships by actively engaging with our network members. This creates the confidence and collaboration that is necessary for our continued success. We believe that our integrity is our greatest asset and we value people over process. We are steadfast in our commitment to the highest ethical principles in all of our business dealings and endeavor to add value in any way we can.
Job Description
We have a PERM position in sunny Tucson, AZ for an ASIC FPGA Designer. There are several positions available at all levels. The job description is below. If you are still available please send an updated resume, your salary requirements, date of availability, and your citizenship status
(***OUR CLIENT CANNOT ACCEPT H1B, H2B, F1, TN1 VISAS OR GREEN CARD CANDIDATES***). We cannot work with outside parties or do C2C.
This position requires the eligibility to obtain a security clearance. Non-US citizens may not be eligible to obtain a security clearance.
Thank you!
Dee Smith
Qualifications
This position requires the eligibility to obtain a security clearance. Non-US citizens may not be eligible to obtain a security clearance. The Defense Industrial Security Clearance Office (DISCO), an agency of the Department of Defense, handles and adjudicates the security clearance process. Security clearance factors include, but are not limited to, allegiance to the US, foreign influence, foreign preference, criminal conduct, security violations and drug involvement. Employment is contingent on other factors, including, but not limited to, background checks and drug screens
Required Skills for Principal Electrical Engineer (ASIC Design)
FPGA ASIC design experience required. Knowledge and experience including:
- Development of design documentation
- Application of configuration management tools
- Application of standard ASIC development design flows and methodologies for SOC design
- Use of VHDL and Verilog
- Use of ARM processor cores and associated peripherals
- ASIC supplier management and technical oversight
- Expert level knowledge of industry standard ASIC development tools
Candidates must have broad technical knowledge and experience and be expert in the design of complex ASICs. Must have written VHDL, simulated, synthesized, placed and routed, integrated and tested designs on target hardware. Candidates must have an understanding and appreciation of technical themes and concepts and the ability to develop solutions independently, but also be able to work with systems engineers, software teams and peers to define requirements. Candidates must be able to develop technical solutions to complex problems that require the regular use of ingenuity and creativity.
Demonstrated experience and success in applying best in class design methodologies and tools is required. Working knowledge of Microsoft Office products required. Candidates must be highly motivated, high performers with excellent verbal and written communication skills and a strong desire to learn and contribute in a fast-paced team environment. Candidates must be able to apply extensive technical expertise, and have knowledge of other disciplines related to FPGA and ASIC design. Ability to perform work without appreciable direction is required. Exceptional communication and leadership skills are required.
Experience working in a distributed design and development environment, including tools and methodologies is required.
Desired Qualifications:
- FPGA design experience or desire to perform FPGA design
- Knowledge and experience in the use of assertions
- UVM/OVM experience
- Cryptographic experience highly desired
Knowledge and experience in the design of FPGA for gigabit serial interfaces, Radio Frequency (RF) and Electro-Optical (EO) DSP, controls, data links, embedded processing and processor interfaces highly desired. Knowledge and demonstrated experience with System Verilog and Unified Verification Methodology highly desired. Knowledge of C programming and scripting languages such as Perl or Python highly desired. Knowledge of embedded systems design using Microblaze, Nios or ARM processors a strong plus. FPGA design experience using a Linux based development environment highly desired.
Required Education:
Bachelor of Science in Electrical Engineering
Desired Education:
Master of Science in Electrical Engineering
ABOUT OUR CLIENT:
14,000 employees
Headquartered in Tucson, Ariz.
World's largest developer, producer and integrator of weapon systems More than 1.5 million missiles produced since 1954
Broad weapons portfolio
Missiles
Smart munitions
Projectiles
Kinetic kill vehicles
Directed energy weapons
Mounted reconnaissance, surveillance and target acquisition
Customers: All U.S. military services; allied forces of more than 50 countries
Additional Information
All your information will be kept confidential according to EEO guidelines.
This position requires the eligibility to obtain a security clearance. Non-US citizens may not be eligible to obtain a security clearance.