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Freelance Asic Rtl Design Engineer Jobs in Tucson, AZ

Design Verification Engineer

Tucson, AZ

$131K - $160K/yr

We are seeking a highly motivated and versatile engineer to join our dynamic Current Sensing ... Contribute to the full IC development lifecycle, including RTL design, synthesis, place and route ...

Design Verification Engineer

Tucson, AZ · On-site

$131K - $160K/yr

We are seeking a highly motivated and versatile engineer to join our dynamic Current Sensing ... Contribute to the full IC development lifecycle, including RTL design, synthesis, place and route ...

Senior FPGA Design Engineer

Tucson, AZ · On-site

$86.80 - $165.20/hr

Lead small teams and mentor junior engineers. * Support internal and external technical reviews ... Experience with FPGA/ASIC design, including VHDL and/or Verilog coding or FPGA/ASIC verification ...

RTL/VHDL experience is a plus. * Experience with high-speed interfaces such as SPI, I2C, CAN, USB ... Familiarity with power design and embedded system integration. * Power electronics, motor control ...

RTL/VHDL experience is a plus. * Experience with high-speed interfaces such as SPI, I2C, CAN, USB ... Familiarity with power design and embedded system integration. * Power electronics, motor control ...

RTL/VHDL experience is a plus. * Experience with high-speed interfaces such as SPI, I2C, CAN, USB ... Familiarity with power design and embedded system integration. * Power electronics, motor control ...

FPGA Engineer with Security Clearance

Tucson, AZ · On-site

$105K - $145K/yr

... • FPGA/ASIC design (VHDL coding) or FPGA/ASIC verification (SystemVerilog coding with UVM) • Xilinx or Microsemi devices and flow tools • Delivering FPGA/ASIC solutions to system level ...

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Freelance Asic Rtl Design Engineer information

See Tucson, AZ salary details

$14

$45

$125

How much do freelance asic rtl design engineer jobs pay per hour?

As of Aug 21, 2026, the average hourly pay for freelance asic rtl design engineer in Tucson, AZ is $45.11, according to ZipRecruiter salary data. Most workers in this role earn between $22.93 and $58.41 per hour, depending on experience, location, and employer.

Are freelance ASIC RTL design engineers in demand?

Freelance ASIC RTL design engineers are in demand due to the growing need for custom chip development in industries like telecommunications, AI, and consumer electronics. Skills in hardware description languages such as Verilog or VHDL, along with experience in FPGA prototyping, enhance employability in this flexible work arrangement.

How much does a Freelance ASIC RTL Design Engineer make?

Freelance ASIC RTL Design Engineers typically earn between $50 and $150 per hour, depending on experience, project complexity, and location. Rates can vary based on expertise in hardware description languages like Verilog or VHDL and familiarity with FPGA or ASIC design tools.

What are the most commonly searched types of Asic Rtl Design Engineer jobs in Tucson, AZ?

The most popular types of Asic Rtl Design Engineer jobs in Tucson, AZ are:

What are popular job titles related to Freelance Asic Rtl Design Engineer jobs in Tucson, AZ?

For Freelance Asic Rtl Design Engineer jobs in Tucson, AZ, the most frequently searched job titles are:

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The top searched job categories for Freelance Asic Rtl Design Engineer jobs in Tucson, AZ are:

Infographic showing various Freelance Asic Rtl Design Engineer job openings in Tucson, AZ as of August 2026, with employment types broken down into 50% Full Time, and 50% Contract. Highlights an 100% In-person job distribution, with an average salary of $93,820 per year, or $45.1 per hour.

$131K - $160K/yr

Full-time

Posted 8 days ago


Job description

Change the world. Love your job. We are seeking a highly motivated and versatile engineer to join our dynamic Current Sensing product line that develops cutting edge Shunt and Hall based mixed signal current sensing ICs. As a key member of our team, you will play a vital role in all phases of IC development, from architectural development, design, DV, tapeout and bring-up. This position offers a unique opportunity to develop expertise in both digital and mixed-signal domains. Job Responsibilities: Design & Implementation: Contribute to the full IC development lifecycle, including RTL design, synthesis, place and route, scan pattern generation, and timing analysis. Verification: Develop and implement robust, scalable verification methodologies for mixed-signal ICs, including testbench creation and automation using DMS and AMS stimulus and checkers. Test Development: Create comprehensive test plans, tests, and simulations at RTL and gate levels using SystemVerilog (SV), VHDL, and the UVM environments. Collaboration & Problem Solving: Work closely with design and system teams to define Design for Verification (DFV) architectures, triage and resolve bugs, and ensure first-pass silicon success. Coverage & Reporting: Drive verification coverage to meet defined goals, track progress, and communicate status, issues, and risks effectively. Continuous Improvement and Automation: Develop and contribute to the evolution of our DV strategy, tools, scripts and methodologies to improve quality, efficiency and automation. Minimum requirements: Atleast 2 years of relevant experience A thorough understanding of digital logic design Familiarity with the Verilog, System Verilog, VHDL language and simulators Ability to solve problems using a systematic approach Preferred qualifications: A good understanding of analog functionality and exposure to analog IC design methods. Understanding and knowledge of analog and digital design principles, including RTL, FSMs, GLS, timing, synchronization, and power domains, mixed-signal and digital verification flow and analog block modeling. Experience with timing verification using Gates+SDF, electrical PVT variation, and timing analysis across analog/digital boundaries Demonstrated strong analytical and problem solving skills Strong verbal and written communication skills Ability to work in teams and collaborate effectively with people in different functions Strong time management skills that enable on-time project delivery Demonstrated ability to build strong, influential relationships Ability to work effectively in a fast-paced and rapidly changing environment Ability to take the initiative and drive for results #J-18808-Ljbffr