FPGA Engineer
$122K - $157K/yr
... and perform code development, simulation, andplace and route. Designs are verified against ... FPGA/ASIC design (VHDL coding) or FPGA/ASIC verification (SystemVerilog coding with UVM) Xilinx or ...
FPGA Engineer
$122K - $157K/yr
... and perform code development, simulation, andplace and route. Designs are verified against ... FPGA/ASIC design (VHDL coding) or FPGA/ASIC verification (SystemVerilog coding with UVM) Xilinx or ...
FPGA Engineer
Tucson, AZ · On-site
$122K - $157K/yr
... and perform code development, simulation, andplace and route. Designs are verified against ... to include the following: • FPGA/ASIC design (VHDL coding) or FPGA/ASIC verification ...
FPGA Engineer
Tucson, AZ · On-site
$122K - $157K/yr
... and perform code development, simulation, andplace and route. Designs are verified against ... to include the following: • FPGA/ASIC design (VHDL coding) or FPGA/ASIC verification ...
Senior FPGA Engineer
Phoenix, AZ · Hybrid
$130K - $180K/yr
Become part of the growing FPGA & ASIC Design Solutions team. As an engineer in this organization ... Test case and test procedure development * Testing in a lab environment * Hands on experience in ...
Quick apply
Senior FPGA Engineer
Phoenix, AZ · Hybrid
$130K - $180K/yr
Become part of the growing FPGA & ASIC Design Solutions team. As an engineer in this organization ... Test case and test procedure development * Testing in a lab environment * Hands on experience in ...
Support and deliver ASIC/Digital tool/flow/methodologysolutions using Cadence tool suites to ... Establish andmaintainquality assurance processes for design flow validation Design Flow Development ...
Support and deliver ASIC/Digital tool/flow/methodologysolutions using Cadence tool suites to ... Establish andmaintainquality assurance processes for design flow validation Design Flow Development ...
FPGA Engineer with Security Clearance
$114K - $157K/yr
... perform code development, simulation, and place and route.  Designs are verified against ... to include the following: • FPGA/ASIC design (VHDL coding) or FPGA/ASIC verification ...
FPGA Engineer with Security Clearance
$114K - $157K/yr
... perform code development, simulation, and place and route.  Designs are verified against ... to include the following: • FPGA/ASIC design (VHDL coding) or FPGA/ASIC verification ...
FPGA Embedded Engineer with Security Clearance
$116K - $149K/yr
... perform code development, simulation, and place and route.  Designs are verified against ... to include the following: • FPGA/ASIC design (VHDL coding) or FPGA/ASIC verification ...
FPGA Embedded Engineer with Security Clearance
$116K - $149K/yr
... perform code development, simulation, and place and route.  Designs are verified against ... to include the following: • FPGA/ASIC design (VHDL coding) or FPGA/ASIC verification ...
FPGA Engineer with Security Clearance
$114K - $157K/yr
... perform code development, simulation, and place and route.  Designs are verified against ... to include the following: • FPGA/ASIC design (VHDL coding) or FPGA/ASIC verification ...
FPGA Engineer with Security Clearance
$114K - $157K/yr
... perform code development, simulation, and place and route.  Designs are verified against ... to include the following: • FPGA/ASIC design (VHDL coding) or FPGA/ASIC verification ...
Support and deliver ASIC/Digital tool/flow/methodology solutions using Cadence tool suites to ... Professional development in digital design methodologies and foundry services * Direct impact on ...
Support and deliver ASIC/Digital tool/flow/methodology solutions using Cadence tool suites to ... Professional development in digital design methodologies and foundry services * Direct impact on ...
Senior FPGA Design Engineer
$116K - $160K/yr
... development, we offer capabilities and opportunity no one else can. Together, we push the ... FPGA/ASIC design, including VHDL and/or Verilog coding or FPGA/ASIC verification using ...
Senior FPGA Design Engineer
$116K - $160K/yr
... development, we offer capabilities and opportunity no one else can. Together, we push the ... FPGA/ASIC design, including VHDL and/or Verilog coding or FPGA/ASIC verification using ...
Senior FPGA Design Engineer
$116K - $160K/yr
... development, we offer capabilities and opportunity no one else can. Together, we push the ... FPGA/ASIC design, including VHDL and/or Verilog coding or FPGA/ASIC verification using ...
Senior FPGA Design Engineer
$116K - $160K/yr
... development, we offer capabilities and opportunity no one else can. Together, we push the ... FPGA/ASIC design, including VHDL and/or Verilog coding or FPGA/ASIC verification using ...
Senior FPGA Design Engineer
$122K - $168K/yr
... development, we offer capabilities and opportunity no one else can. Together, we push the ... FPGA/ASIC design, including VHDL and/or Verilog coding or FPGA/ASIC verification using ...
Senior FPGA Design Engineer
$122K - $168K/yr
... development, we offer capabilities and opportunity no one else can. Together, we push the ... FPGA/ASIC design, including VHDL and/or Verilog coding or FPGA/ASIC verification using ...
Senior FPGA Design Engineer
Tucson, AZ · On-site
$116K - $160K/yr
... development, we offer capabilities and opportunity no one else can. Together, we push the ... FPGA/ASIC design, including VHDL and/or Verilog coding or FPGA/ASIC verification using ...
Senior FPGA Design Engineer
Tucson, AZ · On-site
$116K - $160K/yr
... development, we offer capabilities and opportunity no one else can. Together, we push the ... FPGA/ASIC design, including VHDL and/or Verilog coding or FPGA/ASIC verification using ...
DFT Application Engineer
Phoenix, AZ · On-site
Drive quality improvements in ASIC DFT/DFM and ATPG validation methodology, capability/flow, and ... Professional development in DFT methodologies and foundry services * Direct impact on national ...
DFT Application Engineer
Phoenix, AZ · On-site
Drive quality improvements in ASIC DFT/DFM and ATPG validation methodology, capability/flow, and ... Professional development in DFT methodologies and foundry services * Direct impact on national ...
Drive quality improvements in ASIC DFT/DFM and ATPG validation methodology, capability/flow, and ... Professional development in DFT methodologies and foundry services * Direct impact on national ...
Drive quality improvements in ASIC DFT/DFM and ATPG validation methodology, capability/flow, and ... Professional development in DFT methodologies and foundry services * Direct impact on national ...
Senior FPGA Design Engineer with Security Clearance
Tucson, AZ · On-site
$114K - $157K/yr
... development, we offer capabilities and opportunity no one else can. Together, we push the ... FPGA/ASIC design, including VHDL and/or Verilog coding or FPGA/ASIC verification using ...
Senior FPGA Design Engineer with Security Clearance
Tucson, AZ · On-site
$114K - $157K/yr
... development, we offer capabilities and opportunity no one else can. Together, we push the ... FPGA/ASIC design, including VHDL and/or Verilog coding or FPGA/ASIC verification using ...
We engage at the outset of the weapon system development and follow our designs through deployment ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
We engage at the outset of the weapon system development and follow our designs through deployment ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
Principal Electrical Engineer-FPGA Design- Onsite Tucson, AZ
Phoenix, AZ · On-site
$122K - $168K/yr
We engage at the outset of the weapon system development and follow our designs through deployment ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
Principal Electrical Engineer-FPGA Design- Onsite Tucson, AZ
Phoenix, AZ · On-site
$122K - $168K/yr
We engage at the outset of the weapon system development and follow our designs through deployment ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
We engage at the outset of the weapon system development and follow our designs through deployment ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
We engage at the outset of the weapon system development and follow our designs through deployment ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
Principal Electrical Engineer-FPGA Design- Onsite Tucson, AZ
Tucson, AZ · On-site
$116K - $160K/yr
We engage at the outset of the weapon system development and follow our designs through deployment ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
Principal Electrical Engineer-FPGA Design- Onsite Tucson, AZ
Tucson, AZ · On-site
$116K - $160K/yr
We engage at the outset of the weapon system development and follow our designs through deployment ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
Principal Electrical Engineer-FPGA Design- Onsite Tucson, AZ with Security Clearance
Tucson, AZ · On-site
$114K - $157K/yr
We engage at the outset of the weapon system development and follow our designs through deployment ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
Principal Electrical Engineer-FPGA Design- Onsite Tucson, AZ with Security Clearance
Tucson, AZ · On-site
$114K - $157K/yr
We engage at the outset of the weapon system development and follow our designs through deployment ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
Asic Development Engineer information
What engineer makes $500,000 a year?
An experienced ASIC Development Engineer working in high-demand industries such as semiconductor design or advanced chip development can earn $500,000 or more annually, especially with seniority, specialized skills, and performance bonuses. Such roles often require expertise in hardware description languages, verification tools, and a strong understanding of integrated circuit design.
What is the difference between Asic Development Engineer vs FPGA Design Engineer?
| Aspect | Asic Development Engineer | FPGA Design Engineer |
|---|---|---|
| Required Credentials | Bachelor's or Master's in Electrical Engineering, VLSI, or related fields; knowledge of ASIC design tools | Bachelor's or Master's in Electrical Engineering, Digital Design; familiarity with FPGA development tools |
| Work Environment | Designing and verifying custom silicon chips in semiconductor labs or R&D centers | Developing and testing FPGA-based solutions in hardware labs or embedded systems environments |
| Industry Usage | Used in semiconductor companies, integrated circuit design firms, and tech giants | Common in telecommunications, aerospace, and embedded systems industries |
While both roles involve digital hardware design, Asic Development Engineers focus on creating custom chips for high-performance applications, whereas FPGA Design Engineers work on programmable hardware solutions. Both require strong digital design skills and familiarity with hardware description languages, but their end products and development environments differ.
What engineers make $300,000 a year?
Senior engineers in specialized fields such as ASIC development, software engineering, or data science can earn $300,000 or more annually, especially with extensive experience, advanced skills, and working in high-demand industries or companies. These roles often require advanced degrees, certifications, and expertise in tools like FPGA, VHDL, or Verilog, along with leadership responsibilities.
Are ASIC engineers in demand?
ASIC development engineers are in high demand due to the growth of industries like consumer electronics, telecommunications, and automotive systems that require custom integrated circuits. Skills in hardware description languages such as VHDL or Verilog, along with experience in FPGA prototyping, enhance employability in this field.
How much do ASIC engineers get paid?
ASIC development engineers typically earn between $80,000 and $150,000 annually, depending on experience, location, and company size. Senior engineers with specialized skills or certifications can earn higher salaries, often exceeding $180,000. Compensation may also include bonuses and stock options in some organizations.
What are popular job titles related to Asic Development Engineer jobs in Arizona? For Asic Development Engineer jobs in Arizona, the most frequently searched job titles are:
What job categories do people searching Asic Development Engineer jobs in Arizona look for? The top searched job categories for Asic Development Engineer jobs in Arizona are:
What cities in Arizona are hiring for Asic Development Engineer jobs? Cities in Arizona with the most Asic Development Engineer job openings:
$122K - $157K/yr
Other
Posted 22 days ago
Job description
FPGA Engineer
Develop FPGA designs including: Xilinx, Altera,and Microsemi. Designs are implemented using VHDL
Applications: gigabit serial interfaces, Radio Frequency (RF) and Electro-Optical (EO) DSP, controls, data links, embedded processing and processor interfaces. Designers work with circuit card designers and systems engineers to develop requirements, architect new parts, collaborative modeling of algorithms, partition and perform code development, simulation, andplace and route.
Designs are verified against requirements using both directed test and constrained random methodologies.
Design support is expected from requirements definition through integration and test
Design documentation and configuration management are required.
Responsibilities to Anticipate:
Design and deliver production quality FPGA releases from initial proof of concept up to production
Architect FPGA-based systems to determine parts, interfaces, and Concept of Operations (CONOPS)
Translate system level requirements into FPGA requirements
Design and code in VHDL for reliability and maintainability
Verify designs utilizing self-checking techniques with directed and constrained random tests, while tracking functional and code coverage
Help drive projects and execute to program schedules on time and budget
Create complete documentation including requirements, verification plan, and user's guides
Bachelor of Science in Computer or Electrical Engineering
2-8years+ of experience to include the following:
FPGA/ASIC design (VHDL coding) or FPGA/ASIC verification (SystemVerilog coding with UVM)
Xilinx or Microsemi devices and flow tools
Delivering FPGA/ASIC solutions to system level applications
Hands on experience with integration and debug of FPGA/ASIC devices A US security clearance Pluses
FPGA design experience in one or more of the following areas:
Radar processing techniques
Image processing techniques for visual and infrared sensors
Embedded systems design using ARM, Microblaze, or Nios processors
Gigabit serial interfaces and multi-gigabit transceivers (MGTs)
Constrained random verification in UVM using System Verilog
Verification utilizing emulation platforms, such as Veloce
#CJ
About Associates Systems
Sourced by ZipRecruiter
Industry
Engineering professional services
Company size
1 - 10 Employees
Headquarters location
Dallas, TX, US
Year founded
2002