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Asic Design Salary Jobs (NOW HIRING)

Ayar Labs

Sr. Staff Engineer, ASIC Design

San Jose, CA · On-site

$170K - $223K/yr

Sr. Staff Engineer, ASIC Design Location: San Jose (on-site) Ayar Labs is shattering AI data ... Some knowledge of optics and control systems Salary Range: $180,000 - $223,000 NOTE TO RECRUITERS:

Ayar Labs

Sr. Staff Engineer, ASIC Design

San Jose, CA · On-site

$180K - $223K/yr

Sr. Staff Engineer, ASIC Design Location: San Jose (on-site) Ayar Labs is shattering AI data ... Some knowledge of optics and control systems Salary Range: $180,000 - $223,000 NOTE TO RECRUITERS:

SpaceX

Sr. ASIC Design Engineer (Starshield)

Hawthorne, CA · On-site

$160K - $225K/yr

SR. ASIC DESIGN ENGINEER (STARSHIELD) Starshield leverages SpaceX's Starlink technology and launch ... Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for ...

Cisco

ASIC Design Engineer Technical Lead

San Jose, CA · On-site

$186K - $267K/yr

Bachelor's degree in Electrical or Computer engineering and 8+ years of ASIC Design experience, or ... The starting salary range posted for this position is $186,900.00 to $267,700.00 and reflects the ...

Cisco

ASIC Design Engineer Technical Lead

San Jose, CA · On-site

$186K - $267K/yr

Bachelor's degree in Electrical or Computer engineering and 8+ years of ASIC Design experience, or ... The starting salary range posted for this position is $186,900.00 to $267,700.00 and reflects the ...

Cisco

ASIC Design Verification Engineer

San Jose, CA · On-site

$155K - $222K/yr

Your Impact As an ASIC Design Verification Engineer, you will play a critical role in developing ... The starting salary range posted for this position is $155,000.00 to $222,600.00 and reflects the ...

Nvidia

Senior ASIC Design Engineer

Santa Clara, CA

NVIDIA is looking for an outstanding Senior ASIC Design Engineer to build and implement leading ... Your base salary will be determined based on your location, experience, and the pay of employees in ...

SpaceX

Sr. ASIC Design Engineer (Starshield)

Hawthorne, CA · On-site

$160K - $225K/yr

As an ASIC Design Engineer on the Starshield team, you will be working on advanced development ... Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for ...

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All JobsAsic Design Salary Jobs

Asic Design Salary information

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$94K

$150.2K

$202K

How much do asic design salary jobs pay per year?

As of Aug 17, 2026, the average yearly pay for asic design salary in the United States is $150,195.00, according to ZipRecruiter salary data. Most workers in this role earn between $131,500.00 and $180,000.00 per year, depending on experience, location, and employer.

What is the typical salary for an ASIC design engineer?

The salary for an ASIC (Application-Specific Integrated Circuit) design engineer can vary depending on experience, location, and company size. In the United States, entry-level ASIC design engineers typically earn between $85,000 and $110,000 annually, while those with several years of experience can make upwards of $130,000 to $180,000 or more. Senior or lead ASIC engineers, especially in major tech hubs like Silicon Valley, may see salaries exceeding $200,000, not including bonuses and stock options.

What are the key skills and qualifications needed to thrive as an ASIC design engineer, and why are they important?

To thrive as an ASIC Design Engineer, you need strong expertise in digital and analog circuit design, semiconductor physics, and proficiency with hardware description languages such as VHDL or Verilog, typically supported by a degree in electrical or computer engineering. Familiarity with industry-standard EDA tools like Cadence, Synopsys, or Mentor Graphics, and relevant certifications, is commonly required. Attention to detail, problem-solving skills, and effective teamwork are crucial soft skills in this field. These competencies ensure the successful creation of complex, high-performance integrated circuits that meet stringent design and quality standards.

What are some common challenges ASIC design engineers face when working with cross-functional teams?

ASIC Design Engineers often collaborate with software, hardware, and verification teams throughout the product development cycle. A common challenge is ensuring clear communication of design specifications and constraints to avoid misalignment between teams, which can impact project timelines. Additionally, balancing conflicting requirements or adapting to changing specifications requires flexibility and strong problem-solving skills. Building strong relationships and maintaining regular touchpoints with cross-functional partners are key strategies for overcoming these challenges.

What is the difference between Asic Design Salary vs FPGA Design Engineer Salary?

AspectAsic Design SalaryFPGA Design Engineer Salary
Required CredentialsBachelor's or Master's in Electrical Engineering, VLSI, or related fieldsBachelor's or Master's in Electrical Engineering, VLSI, or related fields
Work EnvironmentDesigning custom chips in semiconductor companies or fabless firmsDeveloping FPGA prototypes in electronics or hardware companies
Industry UsageUsed in high-volume consumer electronics, automotive, and telecomUsed in prototyping, testing, and specialized hardware applications

Both roles require similar educational backgrounds and work in hardware design, but Asic Design Engineers focus on creating custom chips for mass production, while FPGA Design Engineers work on flexible, programmable hardware for testing and development. Salary differences depend on industry demand and project scope.

Are ASIC design engineers in demand?

ASIC design engineers are in high demand due to the growth of semiconductor technology, consumer electronics, and data centers. Skills in hardware description languages like VHDL or Verilog and experience with FPGA or ASIC development tools increase employability in this field.
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Asic Design Salary jobs near you
Infographic showing various Asic Design Salary job openings in the United States as of August 2026, with employment types broken down into 88% Full Time, 10% Part Time, and 2% Contract. Highlights an 91% Physical, 3% Hybrid, and 6% Remote job distribution, with an average salary of $150,195 per year, or $72.2 per hour.

Sr. Staff Engineer, ASIC Design

Ayar Labs

San Jose, CA • On-site

$170K - $223K/yr

Full-time

Re-posted 4 days ago

Job description

Sr. Staff Engineer, ASIC Design
Location: San Jose (on-site)
Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), we are using light instead of electricity to move data faster, further, and with a fraction of the energy needed to fuel the explosive growth of AI models. Backed by industry giants like NVIDIA, AMD and Intel and manufactured in partnership with the world’s leading semiconductor ecosystem, Ayar Labs’ co-packaged optics solution is key to unleashing next-generation AI scale-up architectures.

The ASIC Sr. Staff Engineer is responsible for the design, bring-up, and debug of complex digital subsystems within an electro-optical digital SoC. You will work in a dynamic startup environment as part of a small IC design team, with each team member expected to contribute across a broad range of tasks while gaining new skill sets to grow with the company.
The ideal candidate is a hands-on self-starter who can craft specifications based on input from colleagues, customers, and industry and who can effectively manage his or her own time to take projects to completion with limited supervision and guidance.
KEY RESPONSIBILITIES:
  • Develop detailed digital algorithm specifications in collaboration with analog, photonics, and firmware engineers
  • Develop and optimize RTL in verilog for use in complex electro-optical ASICs
  • Develop models and testbenches for digital and mixed-signal blocks
  • Create clear documentation of their designs to enable backend ASIC engineers to perform physical implementation (clocks and timing constraints, floorplan guidance, testability) and collaborate to ensure timing signoff
  • Bringup, evaluation, and debug of in-house custom silicon using python scripting, firmware, and control systems
  • Contribute to automated design methodologies and flows for ASIC digital design
  • Hands-on work with high-speed interconnects and optical systems
Required Qualifications:
  • BS in Electrical Engineering, Computer Engineering, or related fields
  • 5+ years of work or academic experience in ASIC design
  • History of assuming responsibility for a variety of technical tasks and completing projects independently
  • Mastery of Verilog and SystemVerilog for both RTL design and verification
  • Proficient in ASIC verification (XCelium, VCS, Questa) tools
  • Proficient in low-level programming languages (C, C++)
  • Proficient in Python
  • Working knowledge of digital timing constraints and ASIC tool flows
  • Experience working on digital designs with multiple clock domains and clock dividers
  • Experience with SOC interconnect fabrics (AMBA AXI/AHB/APB)

Preferred Qualifications:
  • MS in Electrical Engineering, Computer Engineering, or related fields
  • Proficient in ASIC synthesis (Genus, Design Compiler) tools
  • Proficient in writing timing constraints and deep understanding of timing analysis
  • Working knowledge integrating custom blocks in a digital-top flow (LEF, lib, etc.)
  • Performed silicon bring-up, debug, and evaluation
  • Working knowledge of FPGAs and/or microcontroller platforms
  • Working knowledge of the Cadence Virtuoso design environment, schematic entry, layout, and simulation
  • Experience with DFT methodologies and flows such as scan insertion, BIST, ATPG, etc
  • Knowledge of high-speed SerDes or SerDes components
  • Some knowledge of optics and control systems
Salary Range: $180,000 - $223,000
NOTE TO RECRUITERS:
Principals only. We are not accepting resumes from recruiters for this position. Remuneration for recruiting activities is only applicable subject to a signed and executed agreement between the parties. Please don’t send candidates to Ayar Labs, and do not contact our managers.

Ayar Labs is an Equal Opportunity Employer and is strongly committed to all policies which will afford equal opportunity employment to all qualified persons without regard to age, sex, national origin, race, color, ethnicity, creed, religion, gender identity, sexual orientation, disability, veteran status, or any other characteristic protected by law. It is the policy of Ayar Labs to provide reasonable accommodation when requested by a qualified applicant or employee with a disability, unless such accommodation would cause an undue hardship. Veterans are more than welcome and encouraged to apply.

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