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Asic Design Engineer Jobs in Washington (NOW HIRING)

3B Staffing LLC

FPGA/ASIC Design Engineer

Reston, VA · On-site

$128K - $176.30K/yr

Technicall/Professional Reporting to the Manager, Engineering (ASIC/FPGA), the Design Engineer will be part of the key ASIC/FPGA design team, responsible for the delivery of FPGA/ASICs for high-speed ...

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$106.5K

$170.1K

$228.8K

How much do asic design engineer jobs pay per year?

As of May 28, 2026, the average yearly pay for asic design engineer in Washington is $170,111.00, according to ZipRecruiter salary data. Most workers in this role earn between $148,900.00 and $203,900.00 per year, depending on experience, location, and employer.

What Does an ASIC Design Engineer Do?

An application specific integrated circuit (ASIC) is an electronic circuit created for a specific purpose, rather than for general use. ASIC design engineers create product design specification (PDS) statements for ASIC, optimize logic design, and create architectural design models. ASIC design engineers often work on a team to deliver ASIC design solutions for standard and complex computing. Knowledge of computer-aided design (CAD) tools, logic simulation, Verilog, and other hardware description languages (HDLs) is integral to career success.

What are the key skills and qualifications needed to thrive as an ASIC Design Engineer, and why are they important?

To thrive as an ASIC Design Engineer, you need a solid background in electrical engineering, digital logic design, and proficiency with hardware description languages like Verilog or VHDL, usually backed by a relevant degree. Familiarity with EDA tools such as Synopsys or Cadence and knowledge of simulation and verification methodologies are typically required. Strong problem-solving abilities, attention to detail, and effective teamwork set outstanding engineers apart in this role. These skills and qualities are vital for delivering complex, high-performance integrated circuits that meet strict specifications and project deadlines.

What are some common challenges faced by ASIC Design Engineers during the design and verification phases?

ASIC Design Engineers often encounter challenges such as meeting strict performance and power constraints while ensuring that the design remains within budget and time limits. Debugging complex logic errors during simulation and verification can be particularly demanding, as small mistakes can have significant downstream effects. Additionally, effective communication with cross-functional teams—including software, hardware, and validation engineers—is essential to resolve integration issues and meet project milestones. Adapting to rapidly evolving tools and technologies is also a key part of the role.

What are ASIC Design Engineers?

ASIC Design Engineers are professionals who design and develop Application-Specific Integrated Circuits (ASICs), which are custom-built semiconductor chips tailored for specific applications or products. They are responsible for the entire design process, including architecture definition, logic design, verification, synthesis, and sometimes physical layout. Their work is crucial in industries like consumer electronics, telecommunications, automotive, and more, ensuring that devices have optimized performance, power efficiency, and functionality for their intended uses.

What is the difference between Asic Design Engineer vs FPGA Design Engineer?

AspectAsic Design EngineerFPGA Design Engineer
CredentialsBachelor's/Master's in Electrical Engineering or Computer EngineeringBachelor's/Master's in Electrical Engineering or Computer Engineering
Work EnvironmentDesigning custom chips for manufacturingDeveloping programmable logic designs for prototyping and deployment
Industry UsageSemiconductor companies, consumer electronics, automotivePrototyping, testing, and specialized hardware applications

Both roles require similar educational backgrounds and often overlap in skills like HDL programming. However, Asic Design Engineers focus on creating chips for mass production, while FPGA Design Engineers work on flexible, reprogrammable hardware for testing and specific applications.

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Asic Design Engineer jobs near you
FPGA/ASIC Design Engineer

FPGA/ASIC Design Engineer

3B Staffing LLC

Reston, VA • On-site

$128K - $176.30K/yr

Full-time

This job post has expired today. Applications are no longer accepted.

Job description

Job Category:
Technicall/Professional
Job Description:
Reporting to the Manager, Engineering (ASIC/FPGA), the Design Engineer will be part of the key ASIC/FPGA design team, responsible for the delivery of FPGA/ASICs for high-speed crypto applications. S/he will architect, implement high speed crypto architectures, on ASICs/Xilinx Zynq/MPSOC class FPGAs, with hands on design/debug with Ethernet, TCP/IP protocols.
L3Harris has state-of-the-art EDA flows/methodologies including Synopsys DC/Primetime/Synplify, Xilinx/Intel/Microchip EDA with HLS, Mentor EDA Family suite : Questa, VIPs, UVM framework, Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), Questa Lint, and Catapult (HLS).
This is a key, high impact role in the organization to ensure robust quality and delivery of communication products for National Security.
Skills/Experience:
Bachelors Degree in Electrical Engineering or equivalent degree, and minimum 4 years of prior relevant experience (or Masters Degree plus 2 years of prior relevant experience) developing, implementing, and verification of high-performance communications/networking ASIC/FPGA products.
Possess an active SECRET Clearance
Experience mapping algorithms and standards (Ethernet, TCP/IP, AXI) to hardware and architecture/system design tradeoffs.
Proficient in VHDL design process and FPGA flow
Knowledge of Ethernet, TCP/IP protocols
Strong logic/board debug, and analytical skills.
Excellent written, verbal, and presentation skills.
A PLUS for prior experience with:
High Level Synthesis (HLS) with Vivado,
Embedded SW C++ (OOP) and System Verilog Assertions (SVA)
Knowledge of high-speed protocols (PCIe, TCP/IP, Ethernet)
VHDL Experience is required for all candidates to be considered.
  • Looking for mid-senior level folks
  • Proficient in VHDL >5 yrs, Xilinx FPGA design EDA- Vivado
  • Must have done hands on multiple complex designs arch/design/verification/Synthesis/STA
  • Big Plus
    • Working with Ethernet protocol (not just instantiating the IP) Is a big plus.
    • Mentor EDA CDC/Lint/AC/RDC

Required Skills:
Derive engineering specifications from system requirements and develop detailed architecture
Execute design (RTL AND/OR HLS (C++ to RTL)) and RTL quality (RDC, CDC, Formal, Lint)
Generate test plans
Perform module level verification, synthesis/STA, Lab debug, SW driven validation on Linux based SOC evaluation boards
Silicon/FPGA bring up, characterization and production ramp/support/collateral
Desired Skills:
Prior experience in Aerospace / Defense
Experience in C++ (OOP)
Experience in Xilinx MPSOC design with writing/debugging with SDKs, BSPs on bare metal/PetaLinux OS.
Experience with High level synthesis (Xilinx Vivado HLS, AND/OR Mentor Calypto).
Experience with Universal Verification Mythology (UVM)
Experience with project leadership and EVM
Degree Requirements:
Bachelors Degree in Electrical Engineering or equivalent degree, and minimum 4 years of prior relevant experience (or Masters Degree plus 2 years of prior relevant experience) developing, implementing, and verification of high-performance communications/networking ASIC/FPGA products.

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