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Intern Asic Design Engineer Jobs in Washington (NOW HIRING)

3B Staffing LLC

FPGA/ASIC Design Engineer

Reston, VA · On-site

$128K - $176K/yr

Technicall/Professional Reporting to the Manager, Engineering (ASIC/FPGA), the Design Engineer will be part of the key ASIC/FPGA design team, responsible for the delivery of FPGA/ASICs for high-speed ...

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Intern Asic Design Engineer information

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How much do intern asic design engineer jobs pay per hour?

As of Jul 26, 2026, the average hourly pay for intern asic design engineer in Washington is $21.95, according to ZipRecruiter salary data. Most workers in this role earn between $16.35 and $24.52 per hour, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as an Intern ASIC Design Engineer, and why are they important?

To thrive as an Intern ASIC Design Engineer, you need a solid background in digital logic design, computer architecture, and a relevant degree in electrical or computer engineering. Familiarity with hardware description languages such as Verilog or VHDL, simulation tools, and EDA software is typically required. Strong analytical thinking, attention to detail, teamwork, and effective communication make an intern stand out in this role. These skills and qualities are crucial for designing reliable, high-performance integrated circuits and collaborating efficiently within engineering teams.

What does an Intern ASIC Design Engineer do?

An Intern ASIC Design Engineer assists in designing, developing, and verifying Application-Specific Integrated Circuits (ASICs) under the guidance of senior engineers. Their responsibilities often include working with hardware description languages like Verilog or VHDL, running simulations, debugging designs, and performing tests to ensure functionality and performance. Interns may also help with documentation, design reviews, and collaborating with cross-functional teams. This role provides hands-on experience in the semiconductor industry and helps build foundational skills for a career in hardware engineering.

What is the difference between Intern Asic Design Engineer vs Intern Digital Design Engineer?

AspectIntern Asic Design EngineerIntern Digital Design Engineer
CredentialsTypically pursuing or holding a degree in Electrical Engineering or Computer EngineeringTypically pursuing or holding a degree in Electrical Engineering or Computer Engineering
Work EnvironmentDesign teams focused on ASIC development, hardware design labs, collaborative projectsDigital circuit design, simulation, verification, and hardware testing environments
Industry UsageUsed in semiconductor companies, integrated circuit design firms, and hardware startupsCommon in semiconductor, electronics, and hardware development companies

Both roles involve working on digital hardware design, often requiring similar educational backgrounds. The main difference lies in the focus: Intern Asic Design Engineers work on the overall ASIC development process, while Intern Digital Design Engineers focus specifically on digital circuit design and verification. Both positions are essential in hardware development and often overlap in skills and work environment.

What types of projects and responsibilities can I expect as an Intern ASIC Design Engineer?

As an Intern ASIC Design Engineer, you can expect to work on a variety of tasks that support the design and verification of integrated circuits. Typical responsibilities include assisting with RTL coding, running simulations, analyzing test results, and documenting design processes. You'll often collaborate closely with senior engineers and cross-functional teams, gaining exposure to state-of-the-art tools and methodologies. This role provides a valuable learning environment where you're encouraged to ask questions, contribute to team discussions, and develop practical skills that are highly valued in the semiconductor industry.
What are the most commonly searched types of Asic Design Engineer jobs in Washington? The most popular types of Asic Design Engineer jobs in Washington are:
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Intern Asic Design Engineer jobs near you
Senior ASIC Physical Design Engineer

Senior ASIC Physical Design Engineer

The Johns Hopkins University Applied Physics Laboratory

Laurel, MD • On-site

Other

Medical, Dental, Vision, Life, Retirement, PTO

Posted 20 days ago

Job description

Description

Do you love building and prototyping robust electrical systems?

Are you passionate about providing real impact to the country's toughest national security problems?

If so, we're looking for someone like you to join our team at APL.

The Miniature Device Technologies Group develops highly customized tools and techniques required to carry out missions around the globe. Whether it be a quick reaction need from the field or the long-term development of a novel capability, we work hand in hand with our government sponsors to conceive and realize solutions to their most challenging problems. We leverage our multi-disciplinary set of capabilities in custom application-specific integrated circuits (ASIC), printed circuit board (PCB), embedded software, field-programmable gate array (FPGA), and signal processing design to create ultra-small, low-power solutions that exceed comparable commercial alternatives.

We are seeking an experienced senior physical design ASIC design engineer, to help us advance the state-of-the-art in miniature systems for a wide range of applications. In this role, you will be responsible for all back-end flow aspects, including synthesis, top-level floor-planning, timing analysis and design partitioning to meet timing requirements, SCAN and BIST insertion, and physical verification checks. You will be working closely with the ASIC design team to identify back-end issues, and assist in addressing these issues, both in the RTL and gate-level phases of the design. You will help explore process selection for new proposals and designs, assessing aspects such as achievable size and power, and availability of the necessary design features and intellectual property (IP.) Additionally, you will perform custom physical design as needed, both to complete custom block layouts, and to perform custom modifications necessary at the top level of the ASIC.

As a Senior ASIC Physical Design Engineer...

  • Your primary responsibility will be digital back-end flow, from synthesis to a completed, verified top-level layout, ready for tapeout submission
  • You will contribute to process selection for new designs and proposals
  • You will floorplan the top-level layout of the digital and mixed-signal ASICs
  • You will perform timing analysis and design partitioning
  • You will perform SCAN and BIST insertion for maximum defect coverage
  • You will work with digital designers to debug and address back-end related RTL and gate-level issues
  • You will perform all physical verification, including DRC, DRC+, MCD, and LVS
  • You will perform custom physical layout
  • You may assist with ASIC design environment enhancements and scripting
  • You will demonstrate initiative by identifying and driving process improvements, and implementing innovative solutions to complex design challenges
  • You will build and maintain strong working relationships with cross-functional teams, including digital design, verification, and software teams
  • You will provide leadership and guidance to junior physical design engineers, and contribute to their growth and development
  • You will collaborate with the team to achieve project goals and objectives, and drive results through effective teamwork and problem-solving
  • You will foster open communication and collaboration with digital designers, junior physical design engineers, and other stakeholders to ensure seamless project execution

Qualifications

You meet our minimum qualifications for the job if you...

  • Possess an Associate's degree in a technical field, or a combination of equivalent level experience/education/certifications.
  • Are skilled at using Cadence ASIC design tools for back-end flow implementation
  • Are skilled at using Siemens Calibre physical verification tools
  • Have 6+ years of experience specifically performing back-end ASIC design
  • Are able to obtain an Interim Secret level security clearance by your start date and can ultimately obtain a Secret level clearance. If selected, you will be subject to a government security clearance investigation and must meet the requirements for access to classified information. Eligibility requirements include U.S. citizenship.

You'll go above and beyond our minimum requirements if you...

  • Have experience with custom physical layout in Cadence Virtuoso
  • Are skilled at using Siemens ASIC design tools for back-end flow implementation
  • Have extensive knowledge and experience in ASIC technology characterization for process selection
  • Hold an active clearance and/or have successfully undergone single-scope background investigations in the past.

#LI-AG1


About Us

Why Work at APL?

The Johns Hopkins University Applied Physics Laboratory (APL) brings world-class expertise to our nation's most critical defense, security, space and science challenges. While we are dedicated to solving complex challenges and pioneering new technologies, what makes us truly outstanding is our culture. We offer a vibrant, welcoming atmosphere where you can bring your authentic self to work, continue to grow, and build strong connections with inspiring teammates.

At APL, we celebrate our differences of perspectives and encourage creativity and bold, new ideas. Our employees enjoy generous benefits, including a robust education assistance program, unparalleled retirement contributions, and a healthy work/life balance. APL's campus is located in the Baltimore-Washington metro area. Learn more about our career opportunities athttps://www.jhuapl.edu/careers.

All qualified applicants will receive consideration for employment without regard to race, creed, color, religion, sex, gender identity or expression, sexual orientation, national origin, age, physical or mental disability, genetic information, veteran status, occupation, marital or familial status, political opinion, personal appearance, or any other characteristic protected by applicable law.APL is committed to providing reasonable accommodation to individuals of all abilities, including those with disabilities. If you require a reasonable accommodation to participate in any part of the hiring process, please contactAccessibility@jhuapl.edu.

The referenced pay range is based on JHU APL's good faith belief at the time of posting. Actual compensation may vary based on factors such as geographic location, work experience, market conditions, education/training and skill level with consideration for internal parity. For salaried employees scheduled to work less than 40 hours per week, annual salary will be prorated based on the number of hours worked. APL may offer bonuses or other forms of compensation per internal policy and/or contractual designation. Additional compensation may be provided in the form of a sign-on bonus, relocation benefits, locality allowance or discretionary payments for exceptional performance. APL provides eligible staff with a comprehensive benefits package including retirement plans, paid time off, medical, dental, vision, life insurance, short-term disability, long-term disability, flexible spending accounts, education assistance, and training and development. Applications are accepted on a rolling basis.


Minimum Rate
$105,000 Annually
Maximum Rate
$290,000 Annually

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