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Analog Layout Engineer Jobs (NOW HIRING)

ACL Digital

Analog Layout Engineer

Austin, TX · On-site

$200.20K/yr

Job Title 10+ years of experience in High-Speed Analog Mixed-Signal layouts Full-custom layout, verification & RC extraction experience. Top-level floorplan, powerplan & integration experience is a ...

Microsoft

Senior Quantum Analog Layout Engineer

Redmond, WA · On-site

$123.80K - $165.20K/yr

As a Senior Quantum Analog Layout Engineer on the Quantum 1st Party Hardware ASIC team, you will play a critical leadership role in advancing Microsoft's quantum analog infrastructure, driving Analog ...

Pacer Group

Memory Layout Engineer

Irvine, CA · On-site

Qualifications: * 7+ years of experience in analog/mixed-signal layout design of deep submicron ... Excellent programming skills in languages: SKILL, Perl; Python is a plus * Strong fundamentals in ...

Apple

Analog Layout Automation Engineer

San Diego, CA · On-site

$214.50K/yr

As an Analog Layout Automation Engineer, you'll convert design concepts into silicon by collaborating with circuit designers and using advanced, including AI-powered, CAD tools to create high ...

Apple

Analog Layout Automation Engineer

Cupertino, CA · On-site

$249.20K/yr

As an Analog Layout Automation Engineer, you'll convert design concepts into silicon by collaborating with circuit designers and using advanced, including AI-powered, CAD tools to create high ...

Apple

Analog Layout Automation Engineer

San Diego, CA · On-site

$214.50K/yr

As an Analog Layout Automation Engineer, you'll convert design concepts into silicon by collaborating with circuit designers and using advanced, including AI-powered, CAD tools to create high ...

Apple

Analog Layout Automation Engineer

Cupertino, CA · On-site

$249.20K/yr

As an Analog Layout Automation Engineer, you'll convert design concepts into silicon by collaborating with circuit designers and using advanced, including AI-powered, CAD tools to create high ...

Apple

Analog Layout Automation Engineer

Austin, TX · On-site

$200.20K/yr

As an Analog Layout Automation Engineer, you'll convert design concepts into silicon by collaborating with circuit designers and using advanced, including AI-powered, CAD tools to create high ...

Apple

Analog Layout Automation Engineer

Cupertino, CA

$121.31K - $213.70K/yr

We're seeking a highly skilled Analog Layout Automation Engineer to contribute to the evolution of Analog/Mixed-Signal (AMS) circuits, covering SerDes, PLLs, and sensors, with a focus on automation ...

Apple

Analog Layout Automation Engineer

San Diego, CA

$115.71K - $203K/yr

We're seeking a highly skilled Analog Layout Automation Engineer to contribute to the evolution of Analog/Mixed-Signal (AMS) circuits, covering SerDes, PLLs, and sensors, with a focus on automation ...

Apple

Analog Layout Automation Engineer

Austin, TX

$154.60K - $274.90K/yr

We're seeking a highly skilled Analog Layout Automation Engineer to contribute to the evolution of Analog/Mixed-Signal (AMS) circuits, covering SerDes, PLLs, and sensors, with a focus on automation ...

Apple

RFIC Layout Engineer

San Francisco, CA · On-site

To deliver these radios, our team is responsible for the design of a wide range of RF, analog, and ... As an RFIC Layout Engineer, you will be a key member of a RFIC team, researching, designing and ...

Apple

Analog Layout Automation Engineer

San Diego, CA

$163.30K - $290.10K/yr

We're seeking a highly skilled Analog Layout Automation Engineer to contribute to the evolution of Analog/Mixed-Signal (AMS) circuits, covering SerDes, PLLs, and sensors, with a focus on automation ...

Apple

Analog Layout Automation Engineer

Cupertino, CA

$172.10K - $305.60K/yr

We're seeking a highly skilled Analog Layout Automation Engineer to contribute to the evolution of Analog/Mixed-Signal (AMS) circuits, covering SerDes, PLLs, and sensors, with a focus on automation ...

Apple

Analog Layout Automation Engineer

Austin, TX

$154.60K - $274.90K/yr

We're seeking a highly skilled Analog Layout Automation Engineer to contribute to the evolution of Analog/Mixed-Signal (AMS) circuits, covering SerDes, PLLs, and sensors, with a focus on automation ...

Apple

RFIC Layout Engineer

San Francisco, CA · On-site

To deliver these radios, our team is responsible for the design of a wide range of RF, analog, and ... As an RFIC Layout Engineer, you will be a key member of a RFIC team, researching, designing and ...

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Analog Layout Engineer information

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$77K

$186.2K

$203K

How much do analog layout engineer jobs pay per year?

As of May 30, 2026, the average yearly pay for analog layout engineer in the United States is $186,238.00, according to ZipRecruiter salary data. Most workers in this role earn between $202,000.00 and $202,000.00 per year, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as an Analog Layout Engineer, and why are they important?

To thrive as an Analog Layout Engineer, you need strong knowledge of semiconductor physics, circuit design principles, and experience with analog/mixed-signal layout, typically supported by a degree in electrical engineering or a related field. Proficiency with EDA tools such as Cadence Virtuoso, DRC/LVS verification tools, and familiarity with IC fabrication processes are crucial. Attention to detail, problem-solving, and effective communication are important soft skills for collaborating with design teams and ensuring design accuracy. These skills and qualities are essential for creating high-performance, manufacturable integrated circuits that meet stringent specifications and timelines.

What are some common challenges Analog Layout Engineers face when collaborating with circuit designers?

Analog Layout Engineers often work closely with circuit designers to translate schematics into physical layouts, which can present challenges such as resolving conflicting design requirements or optimizing for both performance and manufacturability. Miscommunications can occur regarding layout constraints, parasitic effects, or changes in design specifications. Successful collaboration requires clear communication, proactive problem-solving, and regular design reviews to ensure that the final layout meets all electrical, physical, and timing requirements.

What are Analog Layout Engineers?

Analog Layout Engineers are specialized professionals who design the physical layout of analog and mixed-signal integrated circuits (ICs). They translate circuit schematics into detailed geometric representations that can be manufactured on silicon wafers. Their work includes placement and routing of transistors, resistors, capacitors, and interconnects, ensuring optimal performance, area, and reliability. They collaborate closely with circuit designers to meet electrical and physical requirements, and use electronic design automation (EDA) tools to create and verify layouts.

What is the difference between Analog Layout Engineer vs Digital IC Layout Engineer?

AspectAnalog Layout EngineerDigital IC Layout Engineer
Required CredentialsBachelor's or Master's in Electrical Engineering, specialized in analog designBachelor's or Master's in Electrical Engineering, focused on digital design
Work EnvironmentDesigning analog circuits, working closely with circuit designersImplementing digital logic layouts, collaborating with digital design teams
Industry UsageSemiconductor companies, ASIC/FPGA designSemiconductor companies, ASIC/FPGA design
Common Search/ComparisonAnalog Layout Engineer vs Digital IC Layout Engineer

Both roles involve IC layout design within the semiconductor industry, but Analog Layout Engineers focus on analog circuits requiring precise analog signal handling, while Digital IC Layout Engineers work on digital logic circuits. The skills, tools, and design considerations differ, making each role specialized within the chip design process.

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Analog Layout Engineer jobs near you
Infographic showing various Analog Layout Engineer job openings in the United States as of May 2026, with employment types broken down into 95% Full Time, 4% Part Time, and 1% Contract. Highlights an 100% Physical job distribution, with an average salary of $186,238 per year, or $89.5 per hour.
Analog Layout Engineer (Must- High speed Layout & Chip design) _Sanjose, CA(Onsite)_Only Xoriant W2

Analog Layout Engineer (Must- High speed Layout & Chip design) _Sanjose, CA(Onsite)_Only Xoriant W2

Xoriant Corporation

San Jose, CA

$110/hr

Other

Posted 13 hours ago

Job description

Xoriant is an equal opportunity employer. No person shall be excluded from consideration for employment because of race, ethnicity, religion, caste, gender, gender identity, sexual orientation, marital status, national origin, age, disability or veteran status.

TITLE:- Analog Layout Engineer

LOCATION – SanJose, CA

DURATION – 12+ Months (May get extend)

MODE OF INTERVIEW – Zoom/Webex/Onsite

RATE – $110 per hour on W2 (Without Benefits)

JOB DESCRIPTION

Must-

  • High speed Layout design --- 8nm/7nm/6nm/5nm
  • Need someone with strong experience in new chip design
  • In addition to being an individual contributor who can complete assigned tasks(who can bring new ideas, take initiative, and contribute to design improvements.)

As an Analog Layout Engineer, you will be responsible for:

• Layout of Analog / High Speed transceiver circuit blocks such as amplifiers, drivers, ADC, DAC, LDO, PLL, filters, etc. in a timely manner.

• Layout of sensitive active / passive components including resistors, capacitors and inductors.

• Design verification including DRC, LVS, ERC and ANT and extraction.

• Block level floor planning with design engineers.

• Review and update layout for quality including signal integrity, power integrity and parasitic.

Requirements

Associate degree or above with formal training in custom analog layout; BSEE or above preferred The ideal candidate will have the following qualifications:

• 5+ years analog layout experience in deep sub-micron and FinFET processes.

• Experience in floor planning and layout of analog blocks such as amplifiers, drivers, ADC, DAC, LDO, PLL, filters, etc. • Solid knowledge in device structures.

• Understand tradeoffs in matching, coupling, parasitic effects, area, etc.

• Understand causes and preventions of ESD and latch-up.

• Proficient in interpreting verification DRC, LVS, ERC, ANT results.

• Working knowledge of Cadence Virtuoso and Mentor Calibre required.

• Team player with excellent communication skills.

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