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Analog Layout Engineer Jobs in Arizona (NOW HIRING)

Intel

Analog Engineer

Phoenix, AZ

$200K/yr

  • Medical

  • Retirement

  • PTO

As an Analog Circuit Design Engineer, you will be at the forefront of designing and developing ... Collaborate with architecture and layout teams to design circuits that maximize functionality ...

mercury

Senior Substrate Layout Engineer

Phoenix, AZ

$97K - $134K/yr

Understanding of layout techniques in digital, analog, and/or RF designs * Highend package design ... Ability to support electrical engineers with netlisting and componentselection tasks * Experience ...

Mercury Systems

Senior Substrate Layout Engineer

Phoenix, AZ · On-site

$97K - $134K/yr

Understanding of layout techniques in digital, analog, and/or RF designs * Highend package design ... Ability to support electrical engineers with netlisting and componentselection tasks * Experience ...

Mercury Systems

Senior Substrate Layout Engineer

Phoenix, AZ · On-site

$97K - $134K/yr

Understanding of layout techniques in digital, analog, and/or RF designs * High-end package design ... Ability to support electrical engineers with netlisting and component-selection tasks * Experience ...

Intel Corporation

Senior Analog Design Engineer

Phoenix, AZ · On-site

$200K/yr

  • Medical

  • Retirement

  • PTO

The position also involves providing guidance to layout engineers and mentoring junior analog designers as needed. Strong problem-solving skills, teamwork, and a willingness to share knowledge and ...

Intel

Senior Analog Design Engineer

Phoenix, AZ · On-site

$200K/yr

  • Medical

  • Retirement

  • PTO

Create and optimize layouts working closely with layout engineers. Perform circuit analysis ... Technical Leadership Lead analog design projects from specification to silicon validation. Mentor ...

Intel Corporation

Senior Analog Design Engineer

Phoenix, AZ · On-site

$190.61 - $269.10/hr

  • Medical

  • Retirement

  • PTO

The position also involves providing guidance to layout engineers and mentoring junior analog designers as needed. Strong problem-solving skills, teamwork, and a willingness to share knowledge and ...

Cirrus Logic

Analog Design Engineer

Chandler, AZ · On-site

$198K/yr

We are seeking a highly motivated Analog Design Engineer to join a collaborative hardware design ... Lead or support layout implementation, post-layout simulation, and performance optimization ...

Cirrus Logic

Staff Analog Design Engineer

Chandler, AZ · On-site

$198K/yr

We are seeking a highly motivated Analog Design Engineer to join a collaborative hardware design ... Lead or support layout implementation, post-layout simulation, and performance optimization ...

Cirrus Logic

Senior Analog Design Engineer

Chandler, AZ · On-site

$198K/yr

We are seeking a highly motivated Analog Design Engineer to join a collaborative hardware design ... Lead or support layout implementation, post-layout simulation, and performance optimization ...

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All JobsAnalog Layout Engineer JobsAnalog Layout Engineer Jobs in Arizona

Analog Layout Engineer information

See Arizona salary details

$71.8K

$173.6K

$189.2K

How much do analog layout engineer jobs pay per year?

As of Aug 15, 2026, the average yearly pay for analog layout engineer in Arizona is $173,553.00, according to ZipRecruiter salary data. Most workers in this role earn between $188,200.00 and $188,200.00 per year, depending on experience, location, and employer.

What is an analog layout engineer?

Analog Layout Engineers are specialized professionals who design the physical layout of analog and mixed-signal integrated circuits (ICs). They translate circuit schematics into detailed geometric representations that can be manufactured on silicon wafers. Their work includes placement and routing of transistors, resistors, capacitors, and interconnects, ensuring optimal performance, area, and reliability. They collaborate closely with circuit designers to meet electrical and physical requirements, and use electronic design automation (EDA) tools to create and verify layouts.

What are some common challenges analog layout engineers face when collaborating with circuit designers?

Analog Layout Engineers often work closely with circuit designers to translate schematics into physical layouts, which can present challenges such as resolving conflicting design requirements or optimizing for both performance and manufacturability. Miscommunications can occur regarding layout constraints, parasitic effects, or changes in design specifications. Successful collaboration requires clear communication, proactive problem-solving, and regular design reviews to ensure that the final layout meets all electrical, physical, and timing requirements.

What are the key skills and qualifications needed to thrive as an analog layout engineer, and why are they important?

To thrive as an Analog Layout Engineer, you need strong knowledge of semiconductor physics, circuit design principles, and experience with analog/mixed-signal layout, typically supported by a degree in electrical engineering or a related field. Proficiency with EDA tools such as Cadence Virtuoso, DRC/LVS verification tools, and familiarity with IC fabrication processes are crucial. Attention to detail, problem-solving, and effective communication are important soft skills for collaborating with design teams and ensuring design accuracy. These skills and qualities are essential for creating high-performance, manufacturable integrated circuits that meet stringent specifications and timelines.

What is the difference between Analog Layout Engineer vs Digital IC Layout Engineer?

AspectAnalog Layout EngineerDigital IC Layout Engineer
Required CredentialsBachelor's or Master's in Electrical Engineering, specialized in analog designBachelor's or Master's in Electrical Engineering, focused on digital design
Work EnvironmentDesigning analog circuits, working closely with circuit designersImplementing digital logic layouts, collaborating with digital design teams
Industry UsageSemiconductor companies, ASIC/FPGA designSemiconductor companies, ASIC/FPGA design
Common Search/ComparisonAnalog Layout Engineer vs Digital IC Layout Engineer

Both roles involve IC layout design within the semiconductor industry, but Analog Layout Engineers focus on analog circuits requiring precise analog signal handling, while Digital IC Layout Engineers work on digital logic circuits. The skills, tools, and design considerations differ, making each role specialized within the chip design process.

What are the most commonly searched types of Analog Layout Engineer jobs in Arizona?

The most popular types of Analog Layout Engineer jobs in Arizona are:

What are popular job titles related to Analog Layout Engineer jobs in Arizona?

For Analog Layout Engineer jobs in Arizona, the most frequently searched job titles are:

What job categories do people searching Analog Layout Engineer jobs in Arizona look for?

The top searched job categories for Analog Layout Engineer jobs in Arizona are:

Analog Layout Engineer jobs near you
Infographic showing various Analog Layout Engineer job openings in Arizona as of August 2026, with employment types broken down into 6% Internship, 78% Full Time, and 16% Contract. Highlights an 94% In-person, and 6% Remote job distribution, with an average salary of $173,553 per year, or $83.4 per hour.

Analog Engineer

Intel

Phoenix, AZ

$200K/yr

Full-time

Medical, Retirement, PTO

Re-posted 13 hours ago

Intel rating

8.7

Company rating: 8.7 out of 10

Based on 147 frontline employees who took The Breakroom Quiz

19th of 157 rated electronics manufacturers

Job description

Job Details:Job Description: 

The Role and Impact
Join Intel's Advanced Design Foundational IP Organization (AD-FIP) within the Design Technology Platform (DTP), a team that is pivotal in shaping the future of analog and mixed-signal IC design. As an Analog Circuit Design Engineer, you will be at the forefront of designing and developing cutting-edge analog circuits in advanced process nodes. Your work will directly impact Intel's ability to deliver the best-in-class foundational IP and product designs that drive innovation across client, server, and networking technologies. Collaborating with cross-functional teams, you will play a critical role in optimizing performance, power, area, and yield of circuits while pushing the boundaries of what is possible in semiconductor technology.
Key Responsibilities

  • Design, develop, and implement analog circuits and mixed-signal IPs, including ADCs, DACs, voltage regulators, and high-speed I/O interfaces.
  • Perform circuit-level design, simulation, and optimization to meet power, performance, area, timing, and yield requirements.
  • Create and validate floorplans, extract chip parameters, and simulate analog behavior models to ensure robust designs.
  • Develop test plans for design verification and evaluate test results to meet specification requirements.
  • Collaborate with architecture and layout teams to design circuits that maximize functionality, robustness, and electrical capabilities.
  • Conduct tape-out activities for analog and mixed-signal circuits, ensuring successful silicon implementation.
  • Analyze and resolve performance and circuit-related issues during design and post-silicon validation phases.
  • Serve as a technical interface to process technology, IP engineers, and product teams, leveraging design insights to influence future process node development.
Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.

Minimum Qualifications

  • Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field and 8+ years of experience in analog and mixed-signal circuit design; or Master's degree with 6+ years of experience; or PhD with 4+ years of experience.

3+ years of experience with the following technical skills

  • Expertise in analog circuit design, simulation, and verification.
  • Proficiency in CMOS technologies and layout understanding for analog circuits.
  • Experience with tape-out processes for analog mixed-signal circuits, including ADCs and DACs.
  • Knowledge of SoC analog layout design checks and methodologies.

Preferred Qualifications

  • Advanced knowledge of high-speed parallel or serial I/O links, clock distribution, or voltage regulator design.
  • Experience with PLLs, bandgap references, inductors, transmission lines, and RF or millimeter-wave circuits.
  • Strong understanding of power delivery networks (PDN) and integrated power regulators.
  • Proven ability to collaborate across teams and influence decisions related to process technology and product development.

Come be a part of Intel's mission to shape the future of technology. Apply today to join a team where innovation, collaboration, and excellence drive the creation of transformative products.

Job Type:Experienced HireShift:Shift 1 (United States of America)Primary Location: US, Oregon, HillsboroAdditional Locations:US, Arizona, Phoenix, US, California, Santa Clara, US, Texas, AustinBusiness group:Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while delighting our customers -- from delivering cutting-edge silicon process and packaging technology leadership for the AI era, enabling our customers to design leadership products, global manufacturing scale and supply chain, through the continuous yield improvements to advanced packaging all the way to final test and assembly. We ensure our foundry customers' products receive our utmost focus in terms of service, technology enablement and capacity commitments. Employees in the Foundry Technology Manufacturing are part of a worldwide factory network that designs, develops, manufactures, and assembly/test packages the compute devices to improve the lives of every person on Earth.Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $164,470.00-269,100.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

*

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

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About Intel

Sourced by ZipRecruiter

Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth

Industry

Manufacturing

Company size

10,000+ Employees

Headquarters location

Santa Clara, CA, US

Year founded

1968

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