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Ai Chip Design Rtl Jobs in Arizona (NOW HIRING)

Intel

Mixed Signal Logic Design Engineer

Phoenix, AZ

... chip designs. This position is at the forefront of innovation, requiring collaboration with cross ... Implement specifications/designs in RTL and coordinate the work of other junior designers to ...

Intel

Mixed Signal Logic Design Engineer

Phoenix, AZ · On-site

... chip designs. This position is at the forefront of innovation, requiring collaboration with cross ... Implement specifications/designs in RTL and coordinate the work of other junior designers to ...

GuideTech LLC

FPGA Design Engineer

Tucson, AZ · On-site

$116K - $160K/yr

Tucson, AZ GuideTech, a subsidiary of Palladyne AI (NASDAQ: PDYN), builds high-performance avionics ... Develop RTL and support simulation, synthesis, place and route, timing closure, hardware ...

Intel

Director, Engineering

Phoenix, AZ · On-site

Partner closely with Architecture, Circuit Design, RTL Design, Verification, Package, Product ... Experience driving AI-enabled design productivity and design automation initiatives.Proven track ...

Intel

Memory Circuit Design Engineer

Phoenix, AZ · On-site

Memory array/IP design, memory circuit innovation, test-chip design. * Pre-Si verification, post-Si ... leadership for the AI era, enabling our customers to design leadership products, global ...

Viasat, Inc.

Hardware Design Engineer

Tempe, AZ · On-site

$164K - $246K/yr

Develop, simulate, and verify FPGA RTL (using SystemVerilog, Verilog, or VHDL) for control, data ... Familiarity with Git, CI/CD practices, and AI development tools (Claude Code, Copilot). Salary ...

Viasat, Inc.

Hardware Design Engineer

Tempe, AZ · On-site

$164K - $246K/yr

Develop, simulate, and verify FPGA RTL (using SystemVerilog, Verilog, or VHDL) for control, data ... Familiarity with Git, CI/CD practices, and AI development tools (Claude Code, Copilot). Salary ...

Viasat

Hardware Design Engineer

Tempe, AZ · On-site

$133 - $247/hr

Develop, simulate, and verify FPGA RTL (using SystemVerilog, Verilog, or VHDL) for control, data ... Familiarity with Git, CI/CD practices, and AI development tools (Claude Code, Copilot). Salary ...

Viasat, Inc.

Hardware Design Engineer

Tempe, AZ

$164K - $246K/yr

Develop, simulate, and verify FPGA RTL (using SystemVerilog, Verilog, or VHDL) for control, data ... Familiarity with Git, CI/CD practices, and AI development tools (Claude Code, Copilot). Salary ...

Intel

Senior CPU Design Verification Engineer

Phoenix, AZ · On-site

$135K - $164K/yr

From personal computing and AI to cloud-scale data centers and edge platforms, our processors power ... Debug and rootcause complex RTL, microarchitecture, and integration issues; drive issues to ...

Intel

Senior CPU Design Verification Engineer

Phoenix, AZ · On-site

$135K - $164K/yr

From personal computing and AI to cloud-scale data centers and edge platforms, our processors power ... Debug and rootcause complex RTL, microarchitecture, and integration issues; drive issues to ...

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Ai Chip Design Rtl information

What is an AI Chip Design RTL engineer?

AI Chip Design RTL (Register Transfer Level) engineers are specialists who design the digital logic for chips used in artificial intelligence applications. They use hardware description languages like Verilog or VHDL to create and validate the architecture and functionality of these chips before they are manufactured. Their work ensures that AI processors are efficient, high-performing, and meet the requirements of modern AI workloads. RTL engineers collaborate closely with verification, software, and hardware teams to optimize chip performance and power consumption.

What skills and qualifications are needed to thrive as an AI Chip Design RTL engineer?

To thrive as an AI Chip Design RTL Engineer, you need a solid background in digital design, computer architecture, and proficiency in Hardware Description Languages (HDLs) like Verilog or VHDL, often supported by a degree in electrical or computer engineering. Experience with simulation tools (e.g., ModelSim, Synopsys), ASIC/FPGA design flows, and relevant certifications are highly valued. Strong problem-solving abilities, attention to detail, and effective teamwork and communication skills help you excel in collaborative and complex design environments. These competencies are crucial for creating efficient, reliable AI hardware that meets performance and power requirements in a fast-evolving field.

What are common challenges faced by AI Chip Design RTL engineers during the verification process?

AI Chip Design RTL engineers often encounter challenges in ensuring their designs meet complex functional and performance requirements, especially given the rapid pace of AI hardware advancements. Verification can be particularly demanding due to the need to simulate and test intricate AI workloads, manage large datasets, and debug subtle timing or logic errors. Collaboration with verification teams, system architects, and software engineers is essential to address these issues efficiently and to ensure seamless integration of the RTL code into the broader chip design. Staying up-to-date with the latest verification tools and methodologies is also crucial for success in this role.

What is the difference between Ai Chip Design Rtl vs Ai Chip Verification Engineer?

AspectAi Chip Design RtlAi Chip Verification Engineer
Primary FocusDeveloping and implementing Register Transfer Level (RTL) code for AI chipsVerifying and validating RTL designs to ensure functionality
Skills RequiredHDL languages (Verilog/VHDL), digital design, FPGA/ASIC knowledgeSimulation, testbench creation, debugging, scripting skills
Work EnvironmentDesign teams, hardware development labs, EDA toolsVerification teams, simulation environments, test setups
CertificationsHardware design certifications, FPGA/ASIC trainingVerification methodologies, UVM, SystemVerilog certifications

While Ai Chip Design Rtl focuses on creating the hardware description code for AI chips, Ai Chip Verification Engineer ensures that the RTL design functions correctly through rigorous testing. Both roles require knowledge of HDL languages and work closely within hardware development teams, but their core responsibilities differ—design versus verification.

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Ai Chip Design Rtl jobs near you
Infographic showing various Ai Chip Design Rtl job openings in Arizona as of August 2026, with employment types broken down into 100% Full Time. Highlights an 100% In-person job distribution.

Senior Synthesis & Place & Route (P&R) Engineer - MRAM Subsystems

Numem Inc.

Arizona City, AZ • On-site

$120 - $180/hr

Other

Posted 3 days ago

New

Job description

Mesa, AZ — Onsite Full-time Physical Design & Emerging Memory Engineering

We are seeking an experienced Synthesis & Place & Route (P&R) Design Engineer specializing in emerging non-volatile memory (NVM) architectures to join our next-generation MRAM Design Team. In this role, you will lead the digital physical implementation (RTL to GDSII) for embedded MRAM (eMRAM) controllers, peripheral digital logic, write/read timing control, and integrated SoC memory subsystems (STT-MRAM / SOT-MRAM).

You will bridge the gap between RTL logic design, high-density MRAM macro integration, and foundry physical implementation playing a vital role in balancing Power, Performance, Area (PPA), and magnetic/thermal integrity at advanced process nodes.

Lead digital physical implementation (RTL to GDSII) for MRAM controllers and subsystems

Drive synthesis, floor planning, P&R, and sign-off for STT-MRAM / SOT-MRAM designs

Balance Power, Performance, Area (PPA) and magnetic/thermal integrity at advanced nodes

Key Responsibilities
  • Lead synthesis and DFT insertion (scan, MBIST/LBIST) for complex digital memory controllers, built-in self-repair (BISR) logic, and specialized Error-Correcting Code (ECC) engines tailored for MRAM reliability.
  • Develop and maintain complex Multi-Corner Multi-Mode (MCMM) timing constraints (SDC) for high-speed read/write interfaces across extreme temperature and voltage ranges.
  • Optimize synthesized netlists to take advantage of MRAM's non-volatile nature for instant-on capabilities and ultra-low leakage power targets.
  • Work closely with custom layout teams to build full chip floor plan comprehending hard macro placement, reset and timing constraints, and package design rules.
  • Execute macro placement and floor planning for dense MRAM arrays, handling unique Backend-of-Line (BEOL) layer stack constraints caused by Magnetic Tunnel Junction (MTJ) module integration.
  • Construct robust Power Delivery Networks (PDN) capable of handling transient current surges and high write-peak currents required during high-speed switching operations.
  • Develop and implement power domain adhering to power domain crossing rules.
  • Drive end-to-end Place & Route tasks, including custom clock tree synthesis (CTS) designed to minimize jitter and skew across dense MRAM macro boundaries.
  • Perform rigorous static and dynamic IR-drop analysis to prevent voltage droop during simultaneous MRAM array write operations.
  • Execute Static Timing Analysis (STA) and timing closure across standard and specialized process-voltage-temperature (PVT) corners.
  • Implement state-retention, power-gating, and multi-voltage methodologies using UPF/CPF to leverage MRAM's zero-standby-power advantage.
  • Drive physical verification (DRC, LVS, ERC, Antenna) to full sign-off, ensuring compliance with specialized eMRAM foundry design rules and BEOL rule sets.
  • Collaborate with foundry CAD teams and circuit designers to resolve macro interface, seal-ring, and layout-dependent effects (LDE).
  • Build and maintain scalable Tcl/Python scripts to refine automated physical design and sign-off flows.
Required Qualifications
  • B.S. or M.S. in Electrical Engineering, Computer Engineering, or a related field.
  • 7+ years of hands-on physical design experience from logical synthesis to GDSII sign-off.
  • Tool Proficiency — Synthesis & DFT: Synopsys Design/Fusion Compiler or Cadence Genus; Tessent / Synopsys DFT.
  • Tool Proficiency — P&R Implementation: Synopsys ICC2 / Fusion Compiler or Cadence Innovus.
  • Tool Proficiency — STA & Power Integrity: Synopsys PrimeTime / RedHawk or Cadence Tempus / Voltus.
  • Tool Proficiency — Physical Verification: Siemens Calibre (DRC/LVS) or Synopsys ICV.
  • Advanced proficiency in Tcl and Python for flow customization and data analysis.
  • Demonstrated experience handling complex physical constraints, macro placement, and high-current power grid design.
Preferred Qualifications
  • Experience with rule sets spanning multiple nodes in the foundry ecosystem.
  • Knowledge and experience in package design constraints.
  • Direct experience with MRAM (STT-MRAM, SOT-MRAM), eMRAM, or other emerging Non-Volatile Memory technologies (ReRAM, PCM).
  • Familiarity with BEOL process integration constraints (e.g., MTJ placement between specific metal layers affecting routing tracks).
  • Experience implementing low-power architectures leveraging non-volatile memory for fast wake-up / deep sleep states.
  • Background in synthesizing and closing timing on heavy mathematical logic such as high-throughput ECC (Reed-Solomon, BCH, LDPC) or security modules (PUF, AES).
Ready to reshape memory for AI?

Join Numem and help eliminate the memory bottleneck powering the next era of AI — from wearables to data center.

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