66 Google Electrical Jobs Hiring Near You

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X Application Instructions: In most instances, this position requires in-person interviews as part of the hiring process.
Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 10 years of experience in technical leadership focusing on one or more critical aspects of silicon design.
• Experience in two or more silicon disciplines, including architecture modeling, logic design, functional verification, DFT, synthesis, place and route, timing analysis, physical verification, or firmware development.
• Experience in developing, and deploying advanced tools and development flows that streamline the silicon lifecycle and improve engineering productivity.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• 15 years of relevant academic and industrial experience in advanced silicon development.
• Experience in identifying the need for a silicon methodology change, developing a solution, and successfully deploying it with impact to more than 25 developers.
• Experience in developing solutions that require bridging knowledge gaps amongst collaborators.
• Experience collaborating in internal company or external ecosystem standardization efforts.
• Knowledge of both front-end (architecture, logic design, verification) and back-end (logic synthesis, place-and-route, timing convergence, physical verification) silicon development processes.

About the job
In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
As a Staff CAD Engineer, Silicon Design Environment, you collaborate closely with domain experts across the silicon development spectrum and leverage your experience to deliver the development environment that enables building the chips powering the next generation of Google Cloud systems. You possess excellent communication and collaboration skills, expertise in refining ambiguous intent into engaging solutions, and rally others to develop or deploy them.
The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.
We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.
Individual pay is determined by factors including job-related skills, experience, and relevant education or training.
US: $192000 - $278000 (USD) 20% bonus target equity benefits
Learn more about benefits at Google .
Responsibilities

• Leverage the understanding of the phases of silicon development to flesh out the architecture and lead development and deployment of the overall CI2 design environment as a coherent system composed of first-party and third-party tools, industry-standard and Google-specific APIs/data formats and the scalable design flows.
• Collaborate with technical leaders across CI2 sites to identify opportunities for evolutionary and revolutionary tooling and methodology changes to enable convergence on a shared design environment.
• Engage with other Alphabet teams, DeepMind, and Core teams to ensure CI2 stays at the forefront of advanced silicon development.
• Ensure developed technologies optimize for project iteration speed while achieving the planned power, performance, cost, and quality metrics.
• Partner with other members of the tools and methodologies team to apply procedural and AI-first approaches to improve efficiency.

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