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60 Altera Physical Design Engineer Jobs Hiring Near You

Altera

DFT Architect

San Jose, CA

$187K - $270K/yr

Job Details: About Altera At AlteraTM, our independence as the world's largest pure-play FPGA ... Collaborate with architecture, RTL, physical design, timing, validation, and product engineering ...

Altera

ML/AI Timing and Power Flow Expert

San Jose, CA · On-site

$127.40K - $184.40K/yr

About Altera At Altera, we are shaping the future of programmable logic by delivering high ... This is a highly visible, cross-functional position working closely with design, physical design ...

Altera

FPGA Compiler Software Engineer

Toronto, ON

CA$135/hr

Experience developing EDA/CAD optimization algorithms for FPGAs or ASICs * Experience with Altera ... age, physical or mental disability, medical condition, genetic information, military and veteran ...

Altera

Director of Foundry Engineering

San Jose, CA

$209.50K - $303.25K/yr

Why Altera * Lead foundry strategy for cutting-edge FPGA and programmable technologies * Partner with world-class silicon, design, and product teams * Influence long-term manufacturing and technology ...

Altera

FPGA Software Engineer Intern

Toronto, ON

CA$90K - CA$95K/yr

For decades, Altera has been at the forefront of programmable logic technology. Our commitment to ... Estimated Salary Range: $90K - $95K CAD We use artificial intelligence to screen, assess, or select ...

Altera Corporation

DFT Architect

San Jose, CA · On-site

$187K - $270K/yr

About Altera At Altera™, our independence as the world's largest pure-play FPGA solutions ... Collaborate with architecture, RTL, physical design, timing, validation, and product engineering ...

Altera

Senior Design Automation Engineer

San Jose, CA · On-site

$149.10K - $215.93K/yr

Job Details: About Altera At Altera, our independence as the world's largest pureplay FPGA ... age, physical or mental disability, medical condition, genetic information, military and veteran ...

Altera

FPGA Development Tools Engineer

San Jose, CA · On-site

$152.40K - $195.70K/yr

... role in bringing Altera's next-generation FPGA devices to Quartus Prime, our flagship design ... age, physical or mental disability, medical condition, genetic information, military and veteran ...

Altera

Senior Design Automation Engineer

San Jose, CA · On-site

$149.10K - $215.93K/yr

Job Details: About Altera At AlteraTM, our independence as the world's largest pure-play FPGA ... About the Role Altera is seeking a Senior Design Automation Engineer to join our Design Methodology ...

Altera

Machine Learning Engineer

Toronto, ON · On-site

CA$172.10 - CA$253.70/hr

... design ML models,optimizeinference pipelines, and contribute to the evolution of Altera ... age, physical or mental disability, medical condition, genetic information, military and veteran ...

Altera

$134.80K - $195.10K/yr

For decades, Altera has been at the forefront of programmable logic technology. Our commitment to ... Technical Assistance: Assist customers with: architecture definition, solution evaluation, design ...

Altera

FPGA Development Tools Engineer

San Jose, CA · On-site

$127.40K - $184.40K/yr

... role in bringing Altera's next-generation FPGA devices to Quartus Prime, our flagship design ... If you're excited about solving complex engineering problems and working at the intersection of ...

Altera

FPGA DDR and IO Subsystem Architect

San Jose, CA · On-site

$200.40K - $286K/yr

At Altera, you'll work alongside world-class engineers to architect next-generation silicon ... Lead technical reviews and provide guidance across RTL design, circuit design, verification ...

Altera

FPGA Customer Quality Engineer

San Jose, CA · On-site

$118.90K - $172K/yr

Job Details: About Altera At Altera, our independence as the world's largest pureplay FPGA ... following areas: design, validation, test, quality engineering, lab debug, or applications ...

Altera

$113.80K - $156.80K/yr

... physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any ...

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Altera Jobs Information

What is a Physical Design Engineer job?

A Physical Design Engineer is responsible for transforming logical circuit designs into a physical layout that can be manufactured as an integrated circuit (IC). They focus on key aspects like floor planning, placement, clock tree synthesis (CTS), routing, and timing closure while ensuring power and performance optimization. They work with Electronic Design Automation (EDA) tools and collaborate with front-end designers to meet design specifications. The role requires proficiency in tools such as Cadence, Synopsys, or Mentor Graphics and knowledge of processes like ASIC or SoC design.

What are the key skills and qualifications needed to thrive in the Physical Design Engineer position, and why are they important?

To thrive as a Physical Design Engineer, you need a solid background in electrical engineering, experience with ASIC or SoC design methodologies, and a deep understanding of digital circuit fundamentals. Proficiency with EDA tools like Synopsys, Cadence, or Mentor Graphics, as well as familiarity with scripting languages and industry certifications, is highly valued. Attention to detail, effective teamwork, and strong problem-solving skills are essential soft skills for this role. These qualifications are crucial as they enable efficient chip design, ensure successful project delivery, and foster productive collaboration in complex engineering environments.

What are the typical daily responsibilities of a Physical Design Engineer?

As a Physical Design Engineer, your daily responsibilities typically include taking logical circuit designs and translating them into physical layouts, performing floorplanning, placement, and routing of blocks, and conducting timing closure and verification. You will use specialized EDA tools to ensure that designs meet performance, power, and area requirements, collaborating closely with design, verification, and manufacturing teams. The role also involves resolving design issues, optimizing chip layouts, and preparing design data for fabrication. Working in this position provides exposure to advanced technology nodes and the opportunity to contribute directly to the development of cutting-edge semiconductor products.
What other companies are hiring for Physical Design Engineer jobs?
What are the most popular jobs at Altera?
What are the most popular categories at Altera?
Infographic showing various Physical Design Engineer job openings at Altera in the United States as of May 2026, with employment types broken down into 99% Full Time, and 1% Part Time. Highlights an 89% Physical, and 11% Remote job distribution.
FPGA Digital Design and Verification Engineer-Contract

FPGA Digital Design and Verification Engineer-Contract

Altera

San Jose, CA

$100/hr

Full-time

Posted 18 days ago

Job description

Job Details:
Job Description:
Altera is seeking a highly motivated FPGA Digital Design and Verification Engineer-Contract. This 6 month ACE contract provides hands-on experience working on industry-leading programmable logic devices, SoC platforms, and verification environments. The role is ideal for candidates eager to grow their expertise in RISC-V design, SystemVerilog, UVM-based verification, and digital design methodologies.
You will collaborate with experienced engineers to design, verify, and validate RTL blocks and system-level features used in next-generation FPGA products.
Key Responsibilities
  • RISC-V design
  • Develop and maintain SystemVerilog/UVM-based verification environments for FPGA IPs and subsystems
  • Create self-checking testbenches, constrained-random tests, and functional coverage models
  • Write and debug SystemVerilog Assertions (SVA) to ensure protocol and design correctness
  • Execute and analyze simulations using industry-standard EDA tools (VCS, QuestaSim, ModelSim)
  • Assist in debugging RTL and verification failures, working closely with design engineers
  • Verify common communication protocols (e.g., UART, SPI) and custom interconnects
  • Contribute to documentation of verification plans, test strategies, and results
  • Support FPGA-based systems including AI/ML accelerators, memory interfaces, and SoC components
The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.
$100-105K USD
We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.
Qualifications:
Required Qualifications
  • Bachelor's Degree in Computer or Electrical Engineering or related field
  • 1+ years' experience in Digital Logic Design and Computer Architecture
  • RISC-V and digital design experience
  • Proficiency in SystemVerilog and Verilog
  • Knowledge of UVM, functional coverage, constrained random verification, and assertions
  • Experience using simulation and verification tools such as ModelSim, QuestaSim, or Synopsys VCS
  • Familiarity with Linux-based development environments
  • Ability to debug simulation issues and analyze waveforms effectively
Preferred Qualifications
  • Experience verifying communication protocols (UART, SPI, AXI preferred)
  • Exposure to FPGA tools such as Intel Quartus Prime or Xilinx Vivado
  • Knowledge of SVA or formal verification concepts
  • Programming or scripting experience in Python, Perl, Tcl, or C
  • Exposure to HLS, SoC design, or hardware acceleration for AI/ML workloads

Job Type:
Contract Employee (Fixed Term)
Shift:
Shift 1 (United States of America)
Primary Location:
San Jose, California, United States
Additional Locations:
Posting Statement:

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