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60 Altera Physical Design Engineer Jobs Hiring Near You

Altera

FPGA Silicon Design Engineer

San Jose, CA

$149K - $215K/yr

Job Details: About Altera At Altera, our independence as the world's largest pure-play FPGA ... You will collaborate cross-functionally with architecture, verification, and physical design teams ...

Altera

DSP Design Engineer

San Jose, CA

$142K - $206K/yr

About Altera Altera is a global leader in programmable logic solutions, delivering cutting-edge ... Oversees physical design place & route, and timing and power model generation. You will be ...

Altera Corporation

DSP Design Engineer

San Jose, CA · On-site

$142K - $206K/yr

About Altera Altera is a global leader in programmable logic solutions, delivering cutting-edge ... Oversees physical design place & route, and timing and power model generation. You will be ...

Altera

Analog Circuit Design Engineer

San Jose, CA

$149K - $215K/yr

Job Details: About Altera At Altera, our independence as the world's largest pureplay FPGA ... Collaborate with logic designer, logic verification designer, structural physical design engineers ...

Altera

DFT Design Engineer

San Jose, CA

$149K - $213K/yr

Job Details: About Altera: Accelerating Innovators - Altera provides leadership programmable ... age, physical or mental disability, medical condition, genetic information, military and veteran ...

Altera Corporation

DFT Design Engineer

San Jose, CA · On-site

$149K - $213K/yr

Job Details: About Altera: Accelerating Innovators - Altera provides leadership programmable ... age, physical or mental disability, medical condition, genetic information, military and veteran ...

Altera

Design Verification Engineer

San Jose, CA · On-site

$159K - $194K/yr

Job Details: About Altera At Altera, our independence as the world's largest pureplay FPGA ... physical design teams. Salary Range The pay range below is for Bay Area California only. Actual ...

Altera

Physical AI Architect

San Jose, CA

$133K - $190K/yr

About the Role Altera is seeking a PhD-level Engineer/Physical AI Architect to help define the next generation of Physical AI platforms for robotics, industrial automation, machine vision, and ...

Altera

Design Automation Engineer

San Jose, CA · On-site

$95K - $110K/yr

Job Details: About Altera: Accelerating Innovators - Altera provides leadership programmable ... age, physical or mental disability, medical condition, genetic information, military and veteran ...

Altera Corporation

Physical AI Architect

San Jose, CA · On-site

$133K - $190K/yr

About the Role Altera is seeking a PhD-level Engineer/Physical AI Architect to help define the next generation of Physical AI platforms for robotics, industrial automation, machine vision, and ...

Altera

Senior FPGA Compiler (Router) Engineer

San Jose, CA

$152K - $195K/yr

Altera is a leader in FPGA innovation, delivering programmable solutions that power AI, cloud ... Physical design concepts * Problem Solving: Ability to analyze complex systems and develop scalable ...

Altera Corporation

Design Automation Engineer

San Jose, CA · On-site

$95K - $110K/yr

Job Details: About Altera: Accelerating Innovators - Altera provides leadership programmable ... age, physical or mental disability, medical condition, genetic information, military and veteran ...

Altera

Static Timing Analysis (STA) Engineer

Toronto, ON

CA$102K - CA$149K/yr

Altera is seeking a Static Timing Analysis (STA) Engineer to support timing closure and analysis ... physical design teams. * Constraint Development: Assist in developing and validating timing ...

Altera

FPGA Compiler (Router) Engineer

Toronto, ON

CA$115/hr

Altera is a leader in FPGA innovation, delivering programmable solutions that power AI, cloud ... Physical design concepts Problem Solving: * Ability to analyze complex systems and develop scalable ...

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Infographic showing various Physical Design Engineer job openings at Altera in the United States as of June 2026, with employment types broken down into 98% Full Time, and 2% Part Time. Highlights an 95% Physical, and 5% Remote job distribution.
FPGA Silicon Design Engineer

FPGA Silicon Design Engineer

Altera

San Jose, CA

$149K - $215K/yr

Full-time

Posted 7 days ago

Job description

Job Details:Job Description:

About Altera

At Altera, our independence as the world's largest pure-play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of industry-leading FPGA expertise, our singular mission is to deliver the programmable technologies that help customers differentiate, innovate, and scale across rapidly evolving markets like AI, cloud, networking, and edge. As an independent company, we move faster, invest deeper, and partner more closely-empowering our teams to drive breakthrough innovation and shape the future of the FPGA industry.

About the Role

Join Altera as an FPGA Silicon Design Engineer focused on RTL design. In this role, you will be responsible for developing high-quality logic designs and RTL implementations for next-generation FPGA products. You will collaborate cross-functionally with architecture, verification, and physical design teams to deliver robust, high-performance silicon solutions. This position plays a critical role in enabling scalable, power-efficient FPGA architectures used across a wide range of applications.

Key Responsibilities

  • Develop logic design, register transfer level (RTL) coding, and simulation for FPGA components including cell libraries, functional units, IP blocks, and subsystems.

  • Participate in defining architecture and microarchitecture features of assigned design blocks.

  • Create prototypes, simulate models, and define system requirements for new designs.

  • Prepare and design logic diagrams and RTL code to implement system design and test specifications.

  • Deliver software models to support device-level bring-up, including functionality, timing, and power characteristics.

  • Apply RTL implementation techniques to meet power, performance, and area (PPA) goals in partnership with physical design teams.

  • Review verification plans and ensure proper implementation to validate design features.

  • Debug failing RTL tests, identify root causes, and implement corrective actions to ensure design correctness.

Salary Range

The pay range below is for Bay Area California only. Actual salary may vary based ona number offactors including job location, job-related knowledge, skills, experiences,trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.

$149,100 - $215,925USD

We use artificial intelligence to screen, assess, or select applicants for the position.Applicants must be eligible for any required U.S. export authorizations.

Qualifications:

Minimum Qualifications

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, Physics, Math, or related field and 8+ years of industry experience in FPGA or ASIC design.

  • 8+ years of experience in RTL design and coding using SystemVerilog and/or Verilog for complex digital systems.

  • 8+ years of experience with programming/scripting languages such as Python for design automation, modeling, or verification support.

  • 8+ years of experience in hardware design concepts including logic design, finite state machines, control units, processor subsystems, and network-on-chip (NoC) architectures.

  • 8+ years of experience using industry-standard front-end design tools and flows, including synthesis, static timing analysis (STA), linting (e.g., SpyGlass), and power domain methodologies.

  • 8+ years of experience collaborating with cross-functional teams (verification, physical design) to achieve power, performance, and area (PPA) targets.

Preferred Qualifications

  • Knowledge of Network-on-Chip (NoC) architectures and control processors.

  • Experience contributing to silicon bring-up or post-silicon validation.

  • Experience or knowledge in FPGA configuration controllers

Job Type: RegularShift:Shift 1 (United States of America)Primary Location:San Jose, California, United StatesAdditional Locations:Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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