ZipRecruiter

Log In

Altera
Altera

60 Altera Physical Design Engineer Jobs Hiring Near You

Altera

FPGA Silicon Design Engineer

San Jose, CA · On-site

$149.10K - $215.93K/yr

Job Details: About Altera At Altera, our independence as the world's largest pure-play FPGA ... You will collaborate cross-functionally with architecture, verification, and physical design teams ...

Altera

DSP Design Engineer

San Jose, CA · On-site

$142.60K - $206.50K/yr

About Altera Altera is a global leader in programmable logic solutions, delivering cutting-edge ... Oversees physical design place & route, and timing and power model generation. You will be ...

Altera

DSP Design Engineer

San Jose, CA

$142.60K - $206.50K/yr

About Altera Altera is a global leader in programmable logic solutions, delivering cutting-edge ... Oversees physical design place & route, and timing and power model generation. You will be ...

Altera

FPGA Silicon Design Engineer

San Jose, CA · On-site

$149.10K - $215.93K/yr

Job Details: About Altera At AlteraTM, our independence as the world's largest pure-play FPGA ... You will collaborate cross-functionally with architecture, verification, and physical design teams ...

Altera Corporation

DSP Design Engineer

San Jose, CA · On-site

$142.60K - $206.50K/yr

About Altera Altera is a global leader in programmable logic solutions, delivering cutting-edge ... Oversees physical design place & route, and timing and power model generation. You will be ...

Altera

Job Title Logic Design Engineer Altera, a leader in programmable solutions from cloud to edge ... age, physical or mental disability, medical condition, genetic information, military and veteran ...

Altera

Design Verification Engineer

San Jose, CA · On-site

$159.40K - $194.60K/yr

Job Details: About Altera At Altera, our independence as the world's largest pureplay FPGA ... physical design teams. Salary Range The pay range below is for Bay Area California only. Actual ...

Altera

Design Verification Engineer

San Jose, CA

$142.60K - $206.50K/yr

Job Details: About Altera At AlteraTM, our independence as the world's largest pure-play FPGA ... physical design teams. Salary Range The pay range below is for Bay Area California only. Actual ...

Altera

Senior Design Verification Engineer

San Jose, CA · On-site

$142.60K - $206.50K/yr

Altera is responsible for High-Speed Protocol IP development, which includes participating in high-level product specifications, logic/RTL design and implementation, RTL verification, IP FPGA ...

Altera

$125.80K - $153.60K/yr

What We Build Our team develops and verifies high-speed SerDes IP -- the physical layer technology ... Altera Altera is the world's largest independent, pure-play FPGA company. Our programmable logic ...

Altera

DFT Architect

San Jose, CA · On-site

$187K - $270K/yr

Job Details: About Altera At Altera, our independence as the world's largest pureplay FPGA ... Collaborate with architecture, RTL, physical design, timing, validation, and product engineering ...

Altera

Senior Design Verification Engineer

San Jose, CA · On-site

$142.60K - $206.50K/yr

Job Details: Altera is responsible for High-Speed Protocol IP development, which includes ... age, physical or mental disability, medical condition, genetic information, military and veteran ...

Altera

Director of Foundry Engineering

San Jose, CA · On-site

$209.50K - $303.25K/yr

... with design, product engineering, quality, supply chain, and executive leadership. Why Altera ... age, physical or mental disability, medical condition, genetic information, military and veteran ...

Altera

ML/AI Timing and Power Flow Expert

San Jose, CA · On-site

$127.40K - $184.40K/yr

About Altera At Altera, we are shaping the future of programmable logic by delivering high ... This is a highly visible, cross-functional position working closely with design, physical design ...

next page

Showing results 1-20

All JobsAltera JobsAltera Physical Design Engineer Jobs

Altera Jobs Information

What is a Physical Design Engineer job?

A Physical Design Engineer is responsible for transforming logical circuit designs into a physical layout that can be manufactured as an integrated circuit (IC). They focus on key aspects like floor planning, placement, clock tree synthesis (CTS), routing, and timing closure while ensuring power and performance optimization. They work with Electronic Design Automation (EDA) tools and collaborate with front-end designers to meet design specifications. The role requires proficiency in tools such as Cadence, Synopsys, or Mentor Graphics and knowledge of processes like ASIC or SoC design.

What are the key skills and qualifications needed to thrive in the Physical Design Engineer position, and why are they important?

To thrive as a Physical Design Engineer, you need a solid background in electrical engineering, experience with ASIC or SoC design methodologies, and a deep understanding of digital circuit fundamentals. Proficiency with EDA tools like Synopsys, Cadence, or Mentor Graphics, as well as familiarity with scripting languages and industry certifications, is highly valued. Attention to detail, effective teamwork, and strong problem-solving skills are essential soft skills for this role. These qualifications are crucial as they enable efficient chip design, ensure successful project delivery, and foster productive collaboration in complex engineering environments.

What are the typical daily responsibilities of a Physical Design Engineer?

As a Physical Design Engineer, your daily responsibilities typically include taking logical circuit designs and translating them into physical layouts, performing floorplanning, placement, and routing of blocks, and conducting timing closure and verification. You will use specialized EDA tools to ensure that designs meet performance, power, and area requirements, collaborating closely with design, verification, and manufacturing teams. The role also involves resolving design issues, optimizing chip layouts, and preparing design data for fabrication. Working in this position provides exposure to advanced technology nodes and the opportunity to contribute directly to the development of cutting-edge semiconductor products.
What other companies are hiring for Physical Design Engineer jobs?
What are the most popular jobs at Altera?
What are the most popular categories at Altera?
Infographic showing various Physical Design Engineer job openings at Altera in the United States as of May 2026, with employment types broken down into 99% Full Time, and 1% Part Time. Highlights an 89% Physical, and 11% Remote job distribution.
FPGA Silicon Design Engineer

FPGA Silicon Design Engineer

Altera

San Jose, CA • On-site

$149.10K - $215.93K/yr

Full-time

Posted 12 days ago

Job description

Job Details:Job Description:

About Altera

At Altera, our independence as the world's largest pure-play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of industry-leading FPGA expertise, our singular mission is to deliver the programmable technologies that help customers differentiate, innovate, and scale across rapidly evolving markets like AI, cloud, networking, and edge. As an independent company, we move faster, invest deeper, and partner more closely-empowering our teams to drive breakthrough innovation and shape the future of the FPGA industry.

About the Role

Join Altera as an FPGA Silicon Design Engineer focused on RTL design. In this role, you will be responsible for developing high-quality logic designs and RTL implementations for next-generation FPGA products. You will collaborate cross-functionally with architecture, verification, and physical design teams to deliver robust, high-performance silicon solutions. This position plays a critical role in enabling scalable, power-efficient FPGA architectures used across a wide range of applications.

Key Responsibilities

  • Develop logic design, register transfer level (RTL) coding, and simulation for FPGA components including cell libraries, functional units, IP blocks, and subsystems.

  • Participate in defining architecture and microarchitecture features of assigned design blocks.

  • Create prototypes, simulate models, and define system requirements for new designs.

  • Prepare and design logic diagrams and RTL code to implement system design and test specifications.

  • Deliver software models to support device-level bring-up, including functionality, timing, and power characteristics.

  • Apply RTL implementation techniques to meet power, performance, and area (PPA) goals in partnership with physical design teams.

  • Review verification plans and ensure proper implementation to validate design features.

  • Debug failing RTL tests, identify root causes, and implement corrective actions to ensure design correctness.

Salary Range

The pay range below is for Bay Area California only. Actual salary may vary based ona number offactors including job location, job-related knowledge, skills, experiences,trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.

$149,100 - $215,925USD

We use artificial intelligence to screen, assess, or select applicants for the position.Applicants must be eligible for any required U.S. export authorizations.

Qualifications:

Minimum Qualifications

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, Physics, Math, or related field and 8+ years of industry experience in FPGA or ASIC design.

  • 8+ years of experience in RTL design and coding using SystemVerilog and/or Verilog for complex digital systems.

  • 8+ years of experience with programming/scripting languages such as Python for design automation, modeling, or verification support.

  • 8+ years of experience in hardware design concepts including logic design, finite state machines, control units, processor subsystems, and network-on-chip (NoC) architectures.

  • 8+ years of experience using industry-standard front-end design tools and flows, including synthesis, static timing analysis (STA), linting (e.g., SpyGlass), and power domain methodologies.

  • 8+ years of experience collaborating with cross-functional teams (verification, physical design) to achieve power, performance, and area (PPA) targets.

Preferred Qualifications

  • Knowledge of Network-on-Chip (NoC) architectures and control processors.

  • Experience contributing to silicon bring-up or post-silicon validation.

  • Experience or knowledge in FPGA configuration controllers

Job Type: RegularShift:Shift 1 (United States of America)Primary Location:San Jose, California, United StatesAdditional Locations:Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Apply