$152K - $195K/yr
About Altera At Altera, our independence as the world's largest pureplay FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of ...
$152K - $195K/yr
About Altera At Altera, our independence as the world's largest pureplay FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of ...
$118K - $210K/yr
About Altera At Altera, our independence as the world's largest pureplay FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of ...
$118K - $210K/yr
About Altera At Altera, our independence as the world's largest pureplay FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of ...
CA$129.10 - CA$187/hr
About Altera At Altera, our independence as the world's largest pureplay FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of ...
CA$129.10 - CA$187/hr
About Altera At Altera, our independence as the world's largest pureplay FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of ...
San Jose, CA · On-site
$187 - $270.70/hr
Altera is a leader in FPGA innovation, delivering programmable solutions that power AI, cloud computing, networking, and edge applications. Our compiler and tools teams are at the core of enabling ...
San Jose, CA · On-site
$187 - $270.70/hr
Altera is a leader in FPGA innovation, delivering programmable solutions that power AI, cloud computing, networking, and edge applications. Our compiler and tools teams are at the core of enabling ...
San Jose, CA · On-site
$118K - $210K/yr
About Altera At Alteraâ„¢, our independence as the world's largest pure-play FPGA solutions ... About the Role We are seeking a highly experienced and capable FPGA Customer Quality Engineer (CQE ...
San Jose, CA · On-site
$118K - $210K/yr
About Altera At Alteraâ„¢, our independence as the world's largest pure-play FPGA solutions ... About the Role We are seeking a highly experienced and capable FPGA Customer Quality Engineer (CQE ...
San Jose, CA · On-site
$149K - $215K/yr
About Altera At Alteraâ„¢, our independence as the world's largest pure-play FPGA solutions ... Altera is seeking a FPGA Compiler Engineer (Placer) to join our Compiler team in San Jose, CA. This ...
San Jose, CA · On-site
$149K - $215K/yr
About Altera At Alteraâ„¢, our independence as the world's largest pure-play FPGA solutions ... Altera is seeking a FPGA Compiler Engineer (Placer) to join our Compiler team in San Jose, CA. This ...
$200K - $286K/yr
About Altera Altera is a leading innovator in FPGA technology, delivering programmable solutions that power the world's data-centric applications-from cloud and communications infrastructure to ...
$200K - $286K/yr
About Altera Altera is a leading innovator in FPGA technology, delivering programmable solutions that power the world's data-centric applications-from cloud and communications infrastructure to ...
Altera is a leader in FPGA innovation, delivering programmable solutions that power AI, cloud computing, networking, and edge applications. Our compiler and tools teams are at the core of enabling ...
Altera is a leader in FPGA innovation, delivering programmable solutions that power AI, cloud computing, networking, and edge applications. Our compiler and tools teams are at the core of enabling ...
$152K - $195K/yr
Altera is a leader in FPGA innovation, delivering programmable solutions that power AI, cloud computing, networking, and edge applications. Our compiler and tools teams are at the core of enabling ...
$152K - $195K/yr
Altera is a leader in FPGA innovation, delivering programmable solutions that power AI, cloud computing, networking, and edge applications. Our compiler and tools teams are at the core of enabling ...
San Jose, CA · On-site
$187K - $270K/yr
Altera is a leader in FPGA innovation, delivering programmable solutions that power AI, cloud computing, networking, and edge applications. Our compiler and tools teams are at the core of enabling ...
San Jose, CA · On-site
$187K - $270K/yr
Altera is a leader in FPGA innovation, delivering programmable solutions that power AI, cloud computing, networking, and edge applications. Our compiler and tools teams are at the core of enabling ...
San Jose, CA · On-site
$200K - $286K/yr
About Altera Altera is a leading innovator in FPGA technology, delivering programmable solutions that power the world's data-centric applications-from cloud and communications infrastructure to ...
San Jose, CA · On-site
$200K - $286K/yr
About Altera Altera is a leading innovator in FPGA technology, delivering programmable solutions that power the world's data-centric applications-from cloud and communications infrastructure to ...
$106K - $153K/yr
About Altera At Altera, our independence as the world's largest pureplay FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of ...
$106K - $153K/yr
About Altera At Altera, our independence as the world's largest pureplay FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of ...
$142K - $206K/yr
As Lead DV Engineer focusing on IP Verification & Validation, you will be responsible for carrying ... the Altera FPGA IP product portfolios. The charter of IP verification & validation team is to ...
$142K - $206K/yr
As Lead DV Engineer focusing on IP Verification & Validation, you will be responsible for carrying ... the Altera FPGA IP product portfolios. The charter of IP verification & validation team is to ...
Translate Altera's FPGA/IP capabilities into market relevant narratives for Sales, Engineering, Product Marketing, and Planning * Develop competitive analyses and market landscape updates on Routing ...
Translate Altera's FPGA/IP capabilities into market relevant narratives for Sales, Engineering, Product Marketing, and Planning * Develop competitive analyses and market landscape updates on Routing ...
This role works closely with Sales, Field Applications Engineers, and Product Planning teams to ... Represent Altera in customer briefings, industry forums, and security-focused events * Support RFIs ...
This role works closely with Sales, Field Applications Engineers, and Product Planning teams to ... Represent Altera in customer briefings, industry forums, and security-focused events * Support RFIs ...
San Jose, CA · On-site
$142K - $206K/yr
As Lead DV Engineer focusing on IP Verification & Validation, you will be responsible for carrying ... the Altera FPGA IP product portfolios. The charter of IP verification & validation team is to ...
San Jose, CA · On-site
$142K - $206K/yr
As Lead DV Engineer focusing on IP Verification & Validation, you will be responsible for carrying ... the Altera FPGA IP product portfolios. The charter of IP verification & validation team is to ...
$159K - $231K/yr
About Altera For decades, Altera has been a leader in programmable logic technology, delivering high-performance FPGA, SoC FPGA, and software solutions that enable customers to solve the world's most ...
$159K - $231K/yr
About Altera For decades, Altera has been a leader in programmable logic technology, delivering high-performance FPGA, SoC FPGA, and software solutions that enable customers to solve the world's most ...
San Jose, CA · On-site
$200K - $290K/yr
This role works closely with Sales, Field Applications Engineers, and Product Planning teams to ... Represent Altera in customer briefings, industry forums, and security-focused events * Support RFIs ...
San Jose, CA · On-site
$200K - $290K/yr
This role works closely with Sales, Field Applications Engineers, and Product Planning teams to ... Represent Altera in customer briefings, industry forums, and security-focused events * Support RFIs ...
San Jose, CA · On-site
$149K - $215K/yr
Translate Altera's FPGA/IP capabilities into market relevant narratives for Sales, Engineering, Product Marketing, and Planning * Develop competitive analyses and market landscape updates on Routing ...
San Jose, CA · On-site
$149K - $215K/yr
Translate Altera's FPGA/IP capabilities into market relevant narratives for Sales, Engineering, Product Marketing, and Planning * Develop competitive analyses and market landscape updates on Routing ...
CA$100K - CA$130K/yr
Altera is at the forefront of programmable logic and hardware acceleration. Our mission is to ... FPGA and SoC technologies. The High Level Synthesis (HLS) team at Altera specializes in creating ...
CA$100K - CA$130K/yr
Altera is at the forefront of programmable logic and hardware acceleration. Our mission is to ... FPGA and SoC technologies. The High Level Synthesis (HLS) team at Altera specializes in creating ...
About Altera
At Altera, our independence as the world's largest pureplay FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of industryleading FPGA expertise, our singular mission is to deliver the programmable technologies that help customers differentiate, innovate, and scale across rapidly evolving markets like AI, cloud, networking, and edge. As an independent company, we move faster, invest deeper, and partner more closely-empowering our teams to drive breakthrough innovation and shape the future of the FPGA industry.
Position Overview
Altera is a leader in FPGA innovation, delivering programmable solutions that power AI, cloud computing, networking, and edge applications. Our compiler and tools teams are central to enabling customers to efficiently map complex designs onto advanced FPGA architectures.
Altera is seeking a FPGA Compiler Engineer (Placer) to join our Compiler team in San Jose, CA. This role focuses on developing and optimizing FPGA placement algorithms within the compiler toolchain, directly impacting performance, power efficiency, and overall design quality.
The ideal candidate brings strong expertise in EDA algorithms, large-scale system optimization, and FPGA/ASIC physical design flows, along with a passion for solving complex, performance-critical problems.
Key Responsibilities:
Placement Algorithm Development:
Design, implement, and enhance FPGA placement algorithms to optimize timing, congestion, and resource utilization.
Compiler Flow Enhancement:
Contribute to the end-to-end FPGA compilation flow, working closely with routing, synthesis, and timing teams.
Performance Optimization:
Improve runtime performance, scalability, and quality of results (QoR) for large and complex customer designs.
Timing-Driven Placement:
Develop and refine timing-aware placement strategies to support high-frequency, performance-critical designs.
Cross-Functional Collaboration:
Partner with architecture, routing, and STA teams to align placement strategies with FPGA device capabilities and constraints.
Debug & Analysis:
Analyze placement quality, congestion hotspots, and timing bottlenecks; drive improvements to convergence and design closure.
Toolchain Integration:
Integrate new placement capabilities into the compiler infrastructure and validate across diverse workloads.
Why Join Altera?
Work on core compiler technology that directly impacts FPGA performance and usability
Solve challenging algorithmic problems at scale
Collaborate with world-class teams across architecture, silicon, and software
Salary
The pay range below is for Bay Area California only. Actual salary may vary based ona number offactors including job location, job-related knowledge, skills, experiences,trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.
$149.1K- $215.9KUSD
We use artificial intelligence to screen, assess, or select applicants for the position.Applicants must be eligible for any required U.S. export authorizations.
#CG-1
Qualifications:Minimum Qualifications:
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
6+ years of experience in FPGA/ASIC CAD, EDA tools, or related fields.
Experience in algorithms and data structures (optimization, graph theory, heuristics)
Experience with placement algorithms or physical design flows
Experience in C/C++ and software engineering best practices
Experience with placement techniques (analytical placement, simulated annealing, partitioning, clustering)
Experience with Timing-driven and congestion-driven optimization
Experience in ASIC or FPGA physical design methodologies
Experience in solving complex, large-scale optimization problems with high performance and scalability requirements.
Preferred Qualifications
Experience with FPGA toolchains (e.g., Quartus, Vivado)
Knowledge of FPGA architectures and interconnect fabrics
Familiarity with routing and timing closure techniques
Experience with parallel or distributed algorithms for EDA tools
Scripting experience (e.g., Python, Tcl) for tooling and automation
Sourced by ZipRecruiter
1,001 - 5,000 Employees
San Jose, CA, US
1983