Altera
Altera

60 Altera Physical Design Engineer Jobs Hiring Near You

Altera is seeking a Static Timing Analysis (STA) Engineer to support timing closure and analysis ... physical design teams. * Constraint Development: Assist in developing and validating timing ...

Partner with RTL design, synthesis, physical design (P&R), and architecture teams to identify and ... Experience working in large-scale, distributed engineering environments Why Join Altera * Lead ...

... with design, product engineering, quality, supply chain, and executive leadership. Why Altera ... age, physical or mental disability, medical condition, genetic information, military and veteran ...

Principal NoC IP Micro-Architect

San Jose, CA · On-site

$209.50 - $299.20/hr

You will work closely with architecture, design, verification, software, physical design, and ... Altera: Accelerating InnovatorsAltera provides leadership programmable solutions that are easy-to ...

Job Details: About Altera At Altera, our independence as the world's largest pureplay FPGA ... You will collaborate with architects, IP owners, RTL design engineers, physical design, firmware ...

About Altera At Altera, we are shaping the future of programmable logic by delivering high ... This is a highly visible, cross-functional position working closely with design, physical design ...

Job Details: About Altera At Altera, our independence as the world's largest pureplay FPGA ... You will work closely with architecture, design, verification, software, physical design, and ...

Job Details: About Altera At Altera, our independence as the world's largest pureplay FPGA ... You will partner deeply with architecture, RTL, physical design, validation, product engineering ...

Showing results 41-60

Static Timing Analysis (STA) Engineer

Altera

Toronto, ON

CA$102K - CA$149K/yr

Full-time

Re-posted 16 days ago


Job description

Job Details:Job Description:

Altera is seeking a Static Timing Analysis (STA) Engineer to support timing closure and analysis for advanced FPGA designs. This role will focus on executing timing analysis, debugging violations, and partnering with cross-functional teams to deliver high-performance, power-efficient designs.

The ideal candidate has a strong foundation in STA, experience with modern design flows, and the ability to work effectively in a collaborative engineering environment.

Key Responsibilities

  • Timing Analysis:
    Perform static timing analysis for FPGA designs, including setup/hold checks, constraint validation, and timing signoff support.

  • Timing Closure Support:
    Identify, debug, and resolve timing violations in collaboration with RTL, synthesis, and physical design teams.

  • Constraint Development:
    Assist in developing and validating timing constraints to ensure accurate modeling of design intent.

  • Cross-Functional Collaboration:
    Work closely with design, architecture, and implementation teams to improve timing convergence.

  • Methodology & Flow Execution:
    Apply established STA methodologies and contribute to flow improvements and automation where applicable.

  • Performance Optimization:
    Support optimization efforts for performance, power, and area (PPA) through timing-driven analysis.

Our compensation is designed to reflect the Canadianlabourmarket. The actual salary offered may vary based on several factors, including theposition'slocation, as well as the candidate's experience, skills, training, and job-specific knowledge. In addition to base salary, we offer performance-based incentive opportunities that reward both individual contributions and overall company success.

Estimated Salary Range: $102.9K- $149.1K CAD

We use artificial intelligence to screen, assess, or select applicants for the position.This posting is for an existing vacancy.Canadian work experience is notrequiredfor this role.Applicants must be eligible for any required Canada export authorizations.

Qualifications:

Required Qualifications

  • Experience:
    6+ years of experience in Static Timing Analysis (STA) for ASIC or FPGA designs.

  • Technical Expertise:

    • Solid understanding of STA fundamentals (setup/hold, timing paths, clocking, CDC basics)

    • Experience with industry-standard tools (e.g., PrimeTime or equivalent)

    • Familiarity with synthesis and place & route flows

  • Design Knowledge:
    Working knowledge of:

    • RTL design (Verilog/SystemVerilog)

    • FPGA or ASIC design methodologies

  • Debug & Problem Solving:
    Ability to analyze timing reports, identify root causes, and propose actionable solutions.

  • Education:
    Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.


Preferred Qualifications

  • Experience with FPGA architectures and timing flows

  • Familiarity with advanced process nodes or high-speed designs

  • Scripting experience (e.g., Tcl, Python) for automation

  • Exposure to large-scale or distributed engineering environments

Job Type: RegularShift:Shift 1 (Canada)Primary Location:Toronto, Ontario, CanadaAdditional Locations:Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.