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60 Altera Physical Design Engineer Jobs Hiring Near You

Altera

$125.80K/yr

... manage design engineers across multiple functional domains. You'll be at the forefront of Altera ... age, physical or mental disability, medical condition, genetic information, military and veteran ...

Altera

$134.80K - $195.10K/yr

For decades, Altera has been at the forefront of programmable logic technology. Our commitment to ... Technical Assistance: Assist customers with: architecture definition, solution evaluation, design ...

Altera

FPGA DDR and IO Subsystem Architect

San Jose, CA · On-site

$200.40K - $286K/yr

At Altera, you'll work alongside world-class engineers to architect next-generation silicon ... Lead technical reviews and provide guidance across RTL design, circuit design, verification ...

Altera

Staff/ Senior Staff NPI Debug Engineer

San Jose, CA · On-site

$149.10K - $215K/yr

Staff / Senior Staff NPI Debug Engineer About Altera At AlteraTM, our independence as the world ... Assign clear ownership across Design, Product, Test, Validation, and Manufacturing teams. • ...

Altera

$125.80K/yr

Principal Verification Engineer Altera is looking for a talented and driven Principal Verification ... Collaborate with architects and design engineers to understand IP specifications and define ...

Altera

FPGA Development Tools Engineer

San Jose, CA · On-site

$152.40K - $195.70K/yr

Altera is seeking an FPGA Development Tools Engineer to design, develop, and enhance the next ... age, physical or mental disability, medical condition, genetic information, military and veteran ...

Altera

Senior FPGA Compiler Software Engineer

San Jose, CA · On-site

$178.90K - $259K/yr

Altera develops programmable logic technologies to accelerate innovation for many customers ... Actively researching & developing novel optimization algorithms for our FPGA CAD software tools ...

Altera

Product Development Engineer

San Jose, CA · On-site

$142.60K - $206.50K/yr

About Altera For decades, Altera has been at the forefront of programmable logic technology. Our ... Advance knowledge and understanding of FPGA architecture/design, fab process, test program/content ...

Altera

Senior FPGA Compiler Software Engineer

San Jose, CA · On-site

$178.90K - $259K/yr

Altera develops programmable logic technologies to accelerate innovation for many customers ... Actively researching & developing novel optimization algorithms for our FPGA CAD software tools ...

Altera

Senior Debug Verification Engineer

San Jose, CA · On-site

$149.10K - $215K/yr

Job Details: About Altera At Altera, our independence as the world's largest pureplay FPGA ... About the Role As a Sr. Debug Design Verification Engineer , you will be responsible for Design for ...

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All JobsAltera JobsAltera Physical Design Engineer Jobs

Altera Jobs Information

What is a Physical Design Engineer job?

A Physical Design Engineer is responsible for transforming logical circuit designs into a physical layout that can be manufactured as an integrated circuit (IC). They focus on key aspects like floor planning, placement, clock tree synthesis (CTS), routing, and timing closure while ensuring power and performance optimization. They work with Electronic Design Automation (EDA) tools and collaborate with front-end designers to meet design specifications. The role requires proficiency in tools such as Cadence, Synopsys, or Mentor Graphics and knowledge of processes like ASIC or SoC design.

What are the key skills and qualifications needed to thrive in the Physical Design Engineer position, and why are they important?

To thrive as a Physical Design Engineer, you need a solid background in electrical engineering, experience with ASIC or SoC design methodologies, and a deep understanding of digital circuit fundamentals. Proficiency with EDA tools like Synopsys, Cadence, or Mentor Graphics, as well as familiarity with scripting languages and industry certifications, is highly valued. Attention to detail, effective teamwork, and strong problem-solving skills are essential soft skills for this role. These qualifications are crucial as they enable efficient chip design, ensure successful project delivery, and foster productive collaboration in complex engineering environments.

What are the typical daily responsibilities of a Physical Design Engineer?

As a Physical Design Engineer, your daily responsibilities typically include taking logical circuit designs and translating them into physical layouts, performing floorplanning, placement, and routing of blocks, and conducting timing closure and verification. You will use specialized EDA tools to ensure that designs meet performance, power, and area requirements, collaborating closely with design, verification, and manufacturing teams. The role also involves resolving design issues, optimizing chip layouts, and preparing design data for fabrication. Working in this position provides exposure to advanced technology nodes and the opportunity to contribute directly to the development of cutting-edge semiconductor products.
What other companies are hiring for Physical Design Engineer jobs?
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What are the most popular categories at Altera?
Infographic showing various Physical Design Engineer job openings at Altera in the United States as of May 2026, with employment types broken down into 99% Full Time, and 1% Part Time. Highlights an 89% Physical, and 11% Remote job distribution.
Senior Design Automation Engineer

Senior Design Automation Engineer

Altera Corporation

San Jose, CA • On-site

$149.10K - $215.93K/yr

Full-time

Posted 13 days ago

Job description

Job Details:
Job Description:
About Altera
At Altera™, our independence as the world's largest pure-play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of industry-leading FPGA expertise, our singular mission is to deliver the programmable technologies that help customers differentiate, innovate, and scale across rapidly evolving markets like AI, cloud, networking, and edge. As an independent company, we move faster, invest deeper, and partner more closely-empowering our teams to drive breakthrough innovation and shape the future of the FPGA industry.
About the Role
Altera is seeking a Senior Design Automation Engineer to join our Design Methodology Automation and Infrastructure Team.
The Design Methodology Automation and Infrastructure Team is responsible for building and maintaining the core automation infrastructure that supports Altera's FPGA design flows-from RTL to GDSII. In this senior role, you will drive the architecture, development, and optimization of highly automated, reliable, and scalable flow systems that enhance design productivity and accelerate development cycles for next-generation FPGA products. You will influence technical direction, mentor junior engineers, and collaborate closely with cross-functional teams to deliver world-class automation solutions.
Key Responsibilities:
  • Architect next-generation unified FPGA/SoC design methodologies spanning Front-End, handoff to Backend, Design Verification, Design-For-Test (DFT), Design Data Management/Release flows, and FPGA-specific flows such as Design Intent and Configuration Management.
  • Develop and integrate state-of-the-art EDA solutions, including ML/AI-enhanced tools, flows, and methodologies-sourced externally or developed internally-to create sustainable, scalable automation solutions for multiple chip design programs.
  • Collaborate with design automation technical leads, design domain leads, and domain managers to define and drive new design automation architectures from concept through full production deployment across upcoming product programs.
  • Partner with EDA vendors to evaluate, explore, and extend tool capabilities that improve design quality, shorten turn-around time, and enhance design optimization.
  • Architect, develop, deploy, and maintain advanced design automation flows and methodologies for digital and/or analog design at scale.
  • Lead evaluation, integration, and enhancement of EDA tools, driving improvements in design productivity, efficiency, and quality across multiple design teams.
  • Design and implement robust automation frameworks that reduce manual effort, increase reproducibility, and improve overall design throughput.
  • Identify workflow bottlenecks across design, verification, CAD, and methodology teams and lead cross-functional initiatives to streamline FPGA design execution.
  • Provide deep technical expertise in scripting, tool customization, and flow development for advanced semiconductor design needs.
  • Drive continuous innovation in design automation infrastructure through adoption of new methodologies, technologies, and optimizations.
  • Collaborate with internal and external EDA vendors, owning issue resolution, feature requests, and deployment of next-generation capabilities.
  • Mentor and provide technical leadership to junior engineers within the Design Automation organization.

#LI-MD1
Salary Range
The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.
$149,100 - $215,925 USD
We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.
Qualifications:
Minimum Qualifications:
Bachelor's or Master's in Computer Science, Electrical Engineering, or equivalent, with a minimum of 8+ years of experience in IC Design or Design Automation and experience in the following:
  • Extensive experience with industry-standard EDA tools and hands-on expertise in design methodologies across multiple domains, such as Front-End Logic Design flows, Design Intent and FPGA-specific flows, Design Verification flows, and Design-for-Test (DFT) flows (with Back-End flow knowledge considered a plus).
  • Strong programming skills in Python, Tcl, C-shell, C, C++, or similar languages.
  • Familiarity with ML/AI applications and algorithms and their use in EDA or design methodology optimizations.
  • Proven leadership skills for driving collaborative, cross-functional projects, with strong communication and influencing abilities

Job Type:
Regular
Shift:
Shift 1 (United States of America)
Primary Location:
San Jose, California, United States
Additional Locations:
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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