Design Verification Engineer
Beaverton, OR · On-site
$141K - $172K/yr
... UVM Experience with C/C++, assembly is a plus. Excellent interpersonal and communication skills and the dream to take on diverse challenges.
Design Verification Engineer
Beaverton, OR · On-site
$141K - $172K/yr
... UVM Experience with C/C++, assembly is a plus. Excellent interpersonal and communication skills and the dream to take on diverse challenges.
Design Verification Engineer
$141K - $172K/yr
... like UVM Experience with C/C++, assembly is a plus. Excellent interpersonal and communication skills and the dream to take on diverse challenges. Minimum Qualifications Minimum of BS + 10 years ...
Design Verification Engineer
$141K - $172K/yr
... like UVM Experience with C/C++, assembly is a plus. Excellent interpersonal and communication skills and the dream to take on diverse challenges. Minimum Qualifications Minimum of BS + 10 years ...
Design Verification Engineer
Beaverton, OR · On-site
$141K - $172K/yr
... UVM Experience with C/C++, assembly is a plus Excellent interpersonal and communication skills and the dream to take on diverse challenges
Design Verification Engineer
Beaverton, OR · On-site
$141K - $172K/yr
... UVM Experience with C/C++, assembly is a plus Excellent interpersonal and communication skills and the dream to take on diverse challenges
Principal Logic Design Engineer
Hillsboro, OR · Hybrid
$127K - $236K/yr
UVM Verification experience * Memory (HBM, LPDDR) expertise * AMBA AXI or CHI design experience About Rambus Rambus is a global company that makes industry-leading memory interface chips and Silicon ...
Principal Logic Design Engineer
Hillsboro, OR · Hybrid
$127K - $236K/yr
UVM Verification experience * Memory (HBM, LPDDR) expertise * AMBA AXI or CHI design experience About Rambus Rambus is a global company that makes industry-leading memory interface chips and Silicon ...
Design Verification Engineer
Beaverton, OR · On-site
$141K - $172K/yr
... UVM Experience with C/C++, assembly is a plus Excellent interpersonal skills and the dream to tackle diverse challenges
Design Verification Engineer
Beaverton, OR · On-site
$141K - $172K/yr
... UVM Experience with C/C++, assembly is a plus Excellent interpersonal skills and the dream to tackle diverse challenges
Design Verification Engineer
$141K - $172K/yr
... like UVM Experience with C/C++, assembly is a plus Excellent interpersonal skills and the dream to tackle diverse challenges Minimum Qualifications Minimum of BS + 3 years relevant industry ...
Design Verification Engineer
$141K - $172K/yr
... like UVM Experience with C/C++, assembly is a plus Excellent interpersonal skills and the dream to tackle diverse challenges Minimum Qualifications Minimum of BS + 3 years relevant industry ...
Design Verification Engineer
Beaverton, OR · On-site
$110 - $170/hr
Knowledge of verification methodologies like UVM * Experience with C/C++, assembly is a plus * Excellent interpersonal skills and the dream to tackle diverse challenges Apple is an equal opportunity ...
Design Verification Engineer
Beaverton, OR · On-site
$110 - $170/hr
Knowledge of verification methodologies like UVM * Experience with C/C++, assembly is a plus * Excellent interpersonal skills and the dream to tackle diverse challenges Apple is an equal opportunity ...
Experience with Universal Verification Methodology (UVM), SystemVerilog checkers and scoreboards. Assertion-based verification, Semiformal Verification (SFV). * Perl or Python knowledge. NVIDIA is ...
Experience with Universal Verification Methodology (UVM), SystemVerilog checkers and scoreboards. Assertion-based verification, Semiformal Verification (SFV). * Perl or Python knowledge. NVIDIA is ...
Senior ASIC Design Verification Engineer
OR · On-site +1
$170K - $250K/yr
Build SystemVerilog/UVM test benches, including agents, monitors, scoreboards, checkers, and coverage models. * Write SystemVerilog Assertions (SVA) and integrate formal verification where ...
Senior ASIC Design Verification Engineer
OR · On-site +1
$170K - $250K/yr
Build SystemVerilog/UVM test benches, including agents, monitors, scoreboards, checkers, and coverage models. * Write SystemVerilog Assertions (SVA) and integrate formal verification where ...
... UVM base testbenches Experience in system Verilog assertions or silicon bringup or UPF and low ... verification is a plus Advanced programming skills such as object orientated programming or CPU ...
... UVM base testbenches Experience in system Verilog assertions or silicon bringup or UPF and low ... verification is a plus Advanced programming skills such as object orientated programming or CPU ...
Design Verification Engineer
$184K - $324K/yr
... like UVM Experience with C/C++, assembly is a plus Excellent interpersonal and communication skills and the dream to take on diverse challenges Minimum Qualifications Minimum of BS + 10 years ...
Design Verification Engineer
$184K - $324K/yr
... like UVM Experience with C/C++, assembly is a plus Excellent interpersonal and communication skills and the dream to take on diverse challenges Minimum Qualifications Minimum of BS + 10 years ...
CPU Debug and Power Management Verification Engineer
Beaverton, OR · On-site
$141K/yr
... UVM base testbenches Experience in system Verilog assertions or silicon bringup or UPF and low ... verification efforts for a block/area of the design
CPU Debug and Power Management Verification Engineer
Beaverton, OR · On-site
$141K/yr
... UVM base testbenches Experience in system Verilog assertions or silicon bringup or UPF and low ... verification efforts for a block/area of the design
... UVM base testbenches Experience in system Verilog assertions or silicon bringup or UPF and low ... verification is a plus Advanced programming skills such as object orientated programming or CPU ...
... UVM base testbenches Experience in system Verilog assertions or silicon bringup or UPF and low ... verification is a plus Advanced programming skills such as object orientated programming or CPU ...
CPU Debug and Power Management Verification Engineer
Beaverton, OR · On-site
$143K/yr
... UVM base testbenches Experience in system Verilog assertions or silicon bringup or UPF and low ... verification efforts for a block/area of the design
CPU Debug and Power Management Verification Engineer
Beaverton, OR · On-site
$143K/yr
... UVM base testbenches Experience in system Verilog assertions or silicon bringup or UPF and low ... verification efforts for a block/area of the design
... UVM base testbenches Experience in system Verilog assertions or silicon bringup or UPF and low ... verification is a plus Advanced programming skills such as object orientated programming or CPU ...
... UVM base testbenches Experience in system Verilog assertions or silicon bringup or UPF and low ... verification is a plus Advanced programming skills such as object orientated programming or CPU ...
... UVM base testbenches Experience in system Verilog assertions or silicon bringup or UPF and low ... verification is a plus Advanced programming skills such as object orientated programming or CPU ...
... UVM base testbenches Experience in system Verilog assertions or silicon bringup or UPF and low ... verification is a plus Advanced programming skills such as object orientated programming or CPU ...
CPU Debug and Power Management Verification Engineer
Beaverton, OR · On-site
$141K/yr
... UVM base testbenches Experience in system Verilog assertions or silicon bringup or UPF and low ... verification efforts for a block/area of the design
CPU Debug and Power Management Verification Engineer
Beaverton, OR · On-site
$141K/yr
... UVM base testbenches Experience in system Verilog assertions or silicon bringup or UPF and low ... verification efforts for a block/area of the design
CPU Debug and Power Management Verification Engineer
Beaverton, OR · On-site
$141K/yr
... UVM base testbenches Experience in system Verilog assertions or silicon bringup or UPF and low ... verification efforts for a block/area of the design
CPU Debug and Power Management Verification Engineer
Beaverton, OR · On-site
$141K/yr
... UVM base testbenches Experience in system Verilog assertions or silicon bringup or UPF and low ... verification efforts for a block/area of the design
Design Verification Engineer
$184K - $324K/yr
... like UVM Experience with C/C++, assembly is a plus Excellent interpersonal and communication skills and the dream to take on diverse challenges Minimum Qualifications Minimum of BS + 10 years ...
Design Verification Engineer
$184K - $324K/yr
... like UVM Experience with C/C++, assembly is a plus Excellent interpersonal and communication skills and the dream to take on diverse challenges Minimum Qualifications Minimum of BS + 10 years ...
CPU Debug and Power Management Verification Engineer
Beaverton, OR · On-site
$141K/yr
... UVM base testbenches Experience in system Verilog assertions or silicon bringup or UPF and low ... verification efforts for a block/area of the design
CPU Debug and Power Management Verification Engineer
Beaverton, OR · On-site
$141K/yr
... UVM base testbenches Experience in system Verilog assertions or silicon bringup or UPF and low ... verification efforts for a block/area of the design
Uvm Verification information
What are the key skills and qualifications needed to thrive in the UVM Verification position, and why are they important?
To thrive as a UVM Verification engineer, you need a solid background in digital design fundamentals, SystemVerilog, and deep expertise in the Universal Verification Methodology (UVM), often backed by a degree in Electrical or Computer Engineering. Familiarity with simulation tools such as Mentor Questa or Synopsys VCS, as well as version control systems and UVM-specific certifications, is highly valuable. Strong analytical abilities, attention to detail, teamwork, and effective communication are important soft skills in this field. These competencies ensure robust, efficient verification of complex hardware designs, leading to higher product quality and successful project outcomes.
What are the typical day-to-day responsibilities of a UVM Verification engineer?
As a UVM Verification engineer, your day-to-day tasks generally include developing test benches, writing and executing test cases, analyzing simulation results, and debugging issues using UVM methodologies. You'll collaborate closely with design engineers to understand specifications and verify that the hardware operates as intended, and you may also contribute to code reviews and continuous integration processes. In addition to technical development, regular meetings for planning, status updates, and issue resolution are common. This role offers opportunities to mentor junior team members and stay up to date with the latest verification techniques and tools, fostering both team and personal growth.
What is a UVM Verification?
A UVM Verification job involves verifying the functionality of digital hardware designs using the Universal Verification Methodology (UVM). Engineers in this role create testbenches, write SystemVerilog code, and develop constrained-random and directed tests to validate chip designs. They work closely with design teams to find and debug issues before fabrication, ensuring high-quality and reliable silicon. UVM verification is essential in industries like semiconductors, automotive, and communications to meet performance and reliability standards.
What are the most commonly searched types of Uvm Verification jobs in Oregon?
The most popular types of Uvm Verification jobs in Oregon are:
What are popular job titles related to Uvm Verification jobs in Oregon?
For Uvm Verification jobs in Oregon, the most frequently searched job titles are:
What job categories do people searching Uvm Verification jobs in Oregon look for?
The top searched job categories for Uvm Verification jobs in Oregon are:
What cities in Oregon are hiring for Uvm Verification jobs?
Cities in Oregon with the most Uvm Verification job openings:
$141K - $172K/yr
Full-time
Re-posted 21 days ago
Apple rating
8.0
Based on 677 frontline employees who took The Breakroom Quiz
7th of 30 rated technology retailers
Job description
Does making the next great technology product excite you? Imagine what you could do here. At Apple, our new ideas have a way of becoming great products, services, and customer experiences very quickly. We bring passion and dedication to our job and when you are a part of that team there's no telling what you could accomplish. Design Verification Engineers at Apple are responsible for verifying the functionality and performance of Apple's premier SOCs. This is a critical job within Apple's Hardware Technology and we'd love to have you join us
Description
As part of a very dedicated team you will be at the heart of the chip design effort collaborating with all subject areas (vertical product model). You own ensuring the quality of the SOC or an IP or subsystem. This requires you to review design and architecture specifications and work closely with design & micro-architecture teams. A key component to the job is understanding the functional & performance goals of the design and you use this knowledge to test optimally. You develop test plans, tests & coverage plans as well as define our next generation verification methodology & testbenches. You will actively communicate and collaborate with design, architecture and software to understand the use cases and corner conditions and drive test cases.
The SOC contains many subsystems and IP, so you may be working on one or several of the following types of IP:
- Neural Engine hardware
- DRAM subsystem, memory controller logic
- Encode and Decode systems for ProRes and other codec formats such as VP9, AV1
- Hardware security, including cryptographic algorithm implementations
- High-Speed IO standards such as PCI Express, DisplayPort, MIPI
- Power management and fabric infrastructure
- Memory cache management
- Display Subsystem for variety of panels and products
These are just some examples of the exciting designs that are part of our team. Joining SOC DV allows you to focus deeply on one main IP or expand your breadth as you work on a collection of subsystems. It's up to you!
Minimum Qualifications
Minimum of BS + 10 years relevant industry experience.
Preferred Qualifications
Skilled in many aspects of digital verification such as constrained random verification process, functional coverage, code coverage, assertion methodology & philosophy
Knowledge of SystemVerilog, digital simulation and debug
Knowledge of computer architecture and digital design fundamentals
Good SW programming skills with knowledge of data structures and algorithms
Experience with Python, Perl, or similar scripting language
Ability to work independently to deliver the project goals
Knowledge of verification methodologies like UVM
Experience with C/C++, assembly is a plus.
Excellent interpersonal and communication skills and the dream to take on diverse challenges.
Description
As part of a very dedicated team you will be at the heart of the chip design effort collaborating with all subject areas (vertical product model). You own ensuring the quality of the SOC or an IP or subsystem. This requires you to review design and architecture specifications and work closely with design & micro-architecture teams. A key component to the job is understanding the functional & performance goals of the design and you use this knowledge to test optimally. You develop test plans, tests & coverage plans as well as define our next generation verification methodology & testbenches. You will actively communicate and collaborate with design, architecture and software to understand the use cases and corner conditions and drive test cases.
The SOC contains many subsystems and IP, so you may be working on one or several of the following types of IP:
- Neural Engine hardware
- DRAM subsystem, memory controller logic
- Encode and Decode systems for ProRes and other codec formats such as VP9, AV1
- Hardware security, including cryptographic algorithm implementations
- High-Speed IO standards such as PCI Express, DisplayPort, MIPI
- Power management and fabric infrastructure
- Memory cache management
- Display Subsystem for variety of panels and products
These are just some examples of the exciting designs that are part of our team. Joining SOC DV allows you to focus deeply on one main IP or expand your breadth as you work on a collection of subsystems. It's up to you!
Minimum Qualifications
Minimum of BS + 10 years relevant industry experience.
Preferred Qualifications
Skilled in many aspects of digital verification such as constrained random verification process, functional coverage, code coverage, assertion methodology & philosophy
Knowledge of SystemVerilog, digital simulation and debug
Knowledge of computer architecture and digital design fundamentals
Good SW programming skills with knowledge of data structures and algorithms
Experience with Python, Perl, or similar scripting language
Ability to work independently to deliver the project goals
Knowledge of verification methodologies like UVM
Experience with C/C++, assembly is a plus.
Excellent interpersonal and communication skills and the dream to take on diverse challenges.
About Apple
Sourced by ZipRecruiter
Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it.
Industry
Computer and electronic product manufacturing
Company size
10,000+ Employees
Headquarters location
Cupertino, CA, US
Year founded
1976