Cupertino, CA · On-site
$2.0K/mo
Medical
Dental
Vision
RTL Design Engineer As an RTL Engineer at Etched, you will be critical in ensuring that our AI ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...
Cupertino, CA · On-site
$2.0K/mo
Medical
Dental
Vision
RTL Design Engineer As an RTL Engineer at Etched, you will be critical in ensuring that our AI ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...
Santa Clara, CA · On-site
$180 - $240/hr
We are seeking a Senior ASIC Design Engineer with seasoned experience in the development of high ... Microarchitecture and RTL design * Design reviews * Implementation support * Tapeout * Silicon ...
Santa Clara, CA · On-site
$180 - $240/hr
We are seeking a Senior ASIC Design Engineer with seasoned experience in the development of high ... Microarchitecture and RTL design * Design reviews * Implementation support * Tapeout * Silicon ...
Milpitas, CA · On-site
ASIC / VLSI ENGINEERS - RTL / STA / PD / DV (Senior Level) We are hiring 4 experienced ASIC / VLSI ... RTL Engineer (Networking / Ethernet) * STA Engineer * Physical Design Engineer * Design ...
Quick apply
Milpitas, CA · On-site
ASIC / VLSI ENGINEERS - RTL / STA / PD / DV (Senior Level) We are hiring 4 experienced ASIC / VLSI ... RTL Engineer (Networking / Ethernet) * STA Engineer * Physical Design Engineer * Design ...
Cupertino, CA · On-site
$2.0K/mo
Medical
Dental
Vision
RTL Design Engineer As an RTL Engineer at Etched, you will be critical in ensuring that our AI ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...
Cupertino, CA · On-site
$2.0K/mo
Medical
Dental
Vision
RTL Design Engineer As an RTL Engineer at Etched, you will be critical in ensuring that our AI ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...
We are seeking a Senior ASIC Design Engineer with seasoned experience in the development of high ... The ideal candidate has hands-on experience across the full ASIC development cycle -- from RTL ...
We are seeking a Senior ASIC Design Engineer with seasoned experience in the development of high ... The ideal candidate has hands-on experience across the full ASIC development cycle -- from RTL ...
Be an integral part of the System ASIC Design team to help develop and improve our RTL and SOC designs * Collaborate with architects, ASIC designers, and verification engineers to design ...
Be an integral part of the System ASIC Design team to help develop and improve our RTL and SOC designs * Collaborate with architects, ASIC designers, and verification engineers to design ...
Be an integral part of the System ASIC Design team to help develop and improve our RTL and SOC designs * Collaborate with architects, ASIC designers, and verification engineers to design ...
Be an integral part of the System ASIC Design team to help develop and improve our RTL and SOC designs * Collaborate with architects, ASIC designers, and verification engineers to design ...
Santa Clara, CA · On-site
$175K/yr
The ideal candidate has hands-on experience across the full ASIC development cycle - from RTL ... We are seeking a Senior ASIC Design Engineer with seasonedexperience in the development of high ...
Santa Clara, CA · On-site
$175K/yr
The ideal candidate has hands-on experience across the full ASIC development cycle - from RTL ... We are seeking a Senior ASIC Design Engineer with seasonedexperience in the development of high ...
Sunnyvale, CA · On-site
ASIC/SOC power engineers with experience on tools like PTPX / RTL-A. * We are seeking a highly skilled and motivated Contract Worker for RTL Design and Verification with expertise in power profiling ...
Quick apply
Sunnyvale, CA · On-site
ASIC/SOC power engineers with experience on tools like PTPX / RTL-A. * We are seeking a highly skilled and motivated Contract Worker for RTL Design and Verification with expertise in power profiling ...
San Jose, CA · On-site
$150K - $275K/yr
Medical
Dental
Vision
Job Summary As an RTL Engineer at Etched, you will be critical in ensuring that our AI chips ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...
San Jose, CA · On-site
$150K - $275K/yr
Medical
Dental
Vision
Job Summary As an RTL Engineer at Etched, you will be critical in ensuring that our AI chips ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...
San Jose, CA · On-site
$150K - $275K/yr
Medical
Dental
Vision
Job Summary As an RTL Engineer at Etched, you will be critical in ensuring that our AI chips ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...
Quick apply
San Jose, CA · On-site
$150K - $275K/yr
Medical
Dental
Vision
Job Summary As an RTL Engineer at Etched, you will be critical in ensuring that our AI chips ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...
$129K - $194K/yr
Medical
Dental
Retirement
Description As an ASIC Design Engineer on the Silicon Security team, you will be responsible for the micro-architecture, RTL design and integration of secure subsystems. Your responsibilities will ...
$129K - $194K/yr
Medical
Dental
Retirement
Description As an ASIC Design Engineer on the Silicon Security team, you will be responsible for the micro-architecture, RTL design and integration of secure subsystems. Your responsibilities will ...
$120K - $225K/yr
We're hiring experienced RTL Design Engineers from junior to senior levels to play a key role in designing and implementing the components that will bring our next-generation AI processors to life.
$120K - $225K/yr
We're hiring experienced RTL Design Engineers from junior to senior levels to play a key role in designing and implementing the components that will bring our next-generation AI processors to life.
$194K/yr
ASIC Engineer Location: San Jose, CA Duration: 6 Months Minimum Required Skills ... ASIC Design, FPGA, RTL Design, Chip Architecture, ASIC, Implementation,Synthesis /Conformal ...
$194K/yr
ASIC Engineer Location: San Jose, CA Duration: 6 Months Minimum Required Skills ... ASIC Design, FPGA, RTL Design, Chip Architecture, ASIC, Implementation,Synthesis /Conformal ...
$150K - $277K/yr
Medical
Dental
Retirement
... RTL designs - Working with design verification and formal verification teams to verify ... front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal ...
$150K - $277K/yr
Medical
Dental
Retirement
... RTL designs - Working with design verification and formal verification teams to verify ... front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal ...
$150K - $277K/yr
Medical
Dental
Retirement
... RTL designs - Working with design verification and formal verification teams to verify ... front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal ...
$150K - $277K/yr
Medical
Dental
Retirement
... RTL designs - Working with design verification and formal verification teams to verify ... front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal ...
NVIDIA is seeking ASIC Design Engineers to implement the world's leading SoC's and GPU's. This ... Craft micro-architecture, implement in RTL, and deliver a fully verified, synthesis/timing clean ...
NVIDIA is seeking ASIC Design Engineers to implement the world's leading SoC's and GPU's. This ... Craft micro-architecture, implement in RTL, and deliver a fully verified, synthesis/timing clean ...
Sunnyvale, CA · On-site
... ASIC design. * Experience interacting with software, system hardware, and other cross-functional ... You will design RTL Intellectual Property (IP) with the focus on management and control subsystem ...
Sunnyvale, CA · On-site
... ASIC design. * Experience interacting with software, system hardware, and other cross-functional ... You will design RTL Intellectual Property (IP) with the focus on management and control subsystem ...
$129K - $194K/yr
Medical
Dental
Retirement
... RTL designs - Working with design verification and formal verification teams to verify ... front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal ...
$129K - $194K/yr
Medical
Dental
Retirement
... RTL designs - Working with design verification and formal verification teams to verify ... front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal ...
$184K - $324K/yr
Medical
Dental
Retirement
... RTL designs - Working with design verification and formal verification teams to verify ... front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal ...
$184K - $324K/yr
Medical
Dental
Retirement
... RTL designs - Working with design verification and formal verification teams to verify ... front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal ...
$110.4K - $121.9K
16% of jobs
$121.9K - $133.5K
3% of jobs
$133.5K - $145K
4% of jobs
$148.4K is the 25th percentile. Wages below this are outliers.
$145K - $156.5K
6% of jobs
The median wage is $163.8K / yr.
$156.5K - $168.1K
33% of jobs
$168.1K - $179.6K
3% of jobs
$179.6K - $191.1K
2% of jobs
$198.7K is the 75th percentile. Wages above this are outliers.
$191.1K - $202.6K
12% of jobs
$202.6K - $214.2K
5% of jobs
$214.2K - $225.7K
4% of jobs
$225.7K - $237.2K
12% of jobs
$110.4K
$176.4K
$237.2K
| Aspect | Temporary Asic Rtl Design Engineer | Temporary FPGA Design Engineer |
|---|---|---|
| Primary Focus | Designing RTL code for ASIC chips | Designing FPGA logic and configurations |
| Skills & Certifications | Verilog/VHDL, ASIC design flow, simulation tools | Verilog/VHDL, FPGA development tools, synthesis |
| Work Environment | Semiconductor companies, ASIC design teams | FPGA development labs, prototyping environments |
| Industry Usage | Used in high-volume chip manufacturing | Used for prototyping, testing, and low-volume products |
Both roles involve RTL design using Verilog or VHDL, but the Temporary Asic Rtl Design Engineer focuses on ASIC chip development, while the Temporary FPGA Design Engineer specializes in FPGA-based prototyping and testing. The choice depends on whether the project aims for mass production or flexible, rapid development.
The most popular types of Asic Rtl Design Engineer jobs in Santa Clara, CA are:
For Temporary Asic Rtl Design Engineer jobs in Santa Clara, CA, the most frequently searched job titles are:
The top searched job categories for Temporary Asic Rtl Design Engineer jobs in Santa Clara, CA are:
Cities near Santa Clara, CA with the most Temporary Asic Rtl Design Engineer job openings:
$2.0K/mo
Full-time
Medical, Dental, Vision
Re-posted 21 days ago
About Etched
Etched is building AI chips that are hard-coded for individual model architectures. Our first product (Sohu) only supports transformers, but has an order of magnitude more throughput and lower latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep chain-of-thought reasoning.
RTL Design Engineer
As an RTL Engineer at Etched, you will be critical in ensuring that our AI chips operate correctly and efficiently. You will develop and implement design verification strategies for both our existing and upcoming ASIC designs.
In this role, you will work closely with state-of-the-art architectures for machine learning. You do not need to have experience working with these yet, but you will be willing and able to learn quickly. You will work in a fast-paced environment with a high degree of autonomy, and be responsible for a key part of Etched's success.
Representative projects:
You may be a good fit if you:
Strong candidates may also have experience with:
We encourage you to apply even if you do not believe you meet every single qualification.
How we're different:
Etched believes in the Bitter Lesson. We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model-specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single-model ASICs.
We are a fully in-person team in Cupertino, and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed.
Benefits:
