... engineering teams and the APTD Substrate Integration team to advance substrate building block technologies and manage critical process interactions. • Ensure suppliers meet all Product Control ...
... engineering teams and the APTD Substrate Integration team to advance substrate building block technologies and manage critical process interactions. • Ensure suppliers meet all Product Control ...
Partner closely with on site supplier engineering teams and the APTD Substrate Integration team to advance substrate building block technologies and manage critical process interactions. Ensure ...
Partner closely with on site supplier engineering teams and the APTD Substrate Integration team to advance substrate building block technologies and manage critical process interactions. Ensure ...
Remote Substrate IC Package Design Engineer
Tempe, AZ · On-site +1
$132.30K/yr
The role requires a Bachelor's or Master's degree in Electrical Engineering and at least 5 years of experience in substrate design. We offer competitive salaries, equity opportunities, and a ...
Remote Substrate IC Package Design Engineer
Tempe, AZ · On-site +1
$132.30K/yr
The role requires a Bachelor's or Master's degree in Electrical Engineering and at least 5 years of experience in substrate design. We offer competitive salaries, equity opportunities, and a ...
APTD Substrate Quality Engineer
$71.50K - $92.30K/yr
These products will be volume manufactured within our substrate factory network. The Quality Engineer's (QE) quest to elevate quality standards across our internal factory (CH8) is vital for the ...
APTD Substrate Quality Engineer
$71.50K - $92.30K/yr
These products will be volume manufactured within our substrate factory network. The Quality Engineer's (QE) quest to elevate quality standards across our internal factory (CH8) is vital for the ...
APTD Substrate Quality Engineer
Phoenix, AZ · On-site
$71.50K - $92.30K/yr
These products will be volume manufactured within our substrate factory network. The Quality Engineer's (QE) quest to elevate quality standards across our internal factory (CH8) is vital for the ...
APTD Substrate Quality Engineer
Phoenix, AZ · On-site
$71.50K - $92.30K/yr
These products will be volume manufactured within our substrate factory network. The Quality Engineer's (QE) quest to elevate quality standards across our internal factory (CH8) is vital for the ...
Senior Yield Engineer - Substrate & Advanced Packaging
$101.40K - $139.20K/yr
Intel Foundry Group is seeking a talented Senior Yield Engineer - Substrate & Advanced Packaging to join our Advanced Packaging Technology and Manufacturing team. In this role, you'll be at the ...
Senior Yield Engineer - Substrate & Advanced Packaging
$101.40K - $139.20K/yr
Intel Foundry Group is seeking a talented Senior Yield Engineer - Substrate & Advanced Packaging to join our Advanced Packaging Technology and Manufacturing team. In this role, you'll be at the ...
Senior Yield Engineer - Substrate & Advanced Packaging
Phoenix, AZ · On-site
$103.80K - $142.50K/yr
Intel Foundry Group is seeking a talented Senior Yield Engineer - Substrate & Advanced Packaging to join our Advanced Packaging Technology and Manufacturing team. In this role, you'll be at the ...
Senior Yield Engineer - Substrate & Advanced Packaging
Phoenix, AZ · On-site
$103.80K - $142.50K/yr
Intel Foundry Group is seeking a talented Senior Yield Engineer - Substrate & Advanced Packaging to join our Advanced Packaging Technology and Manufacturing team. In this role, you'll be at the ...
Senior Yield Engineer - Substrate & Advanced Packaging
$103.80K - $142.50K/yr
Intel Foundry Group is seeking a talented Senior Yield Engineer - Substrate & Advanced Packaging to join our Advanced Packaging Technology and Manufacturing team. In this role, you'll be at the ...
Senior Yield Engineer - Substrate & Advanced Packaging
$103.80K - $142.50K/yr
Intel Foundry Group is seeking a talented Senior Yield Engineer - Substrate & Advanced Packaging to join our Advanced Packaging Technology and Manufacturing team. In this role, you'll be at the ...
Lead package material selection, substrate stack-up definition, mechanical modeling, and ... Deep knowledge of Electrical Engineering concepts, circuit extractions and simulation, as well as ...
Lead package material selection, substrate stack-up definition, mechanical modeling, and ... Deep knowledge of Electrical Engineering concepts, circuit extractions and simulation, as well as ...
Silicon Packaging Design Engineer
Phoenix, AZ · On-site
$105.65K - $149.15K/yr
Perform substrate fit and routing studies to establish design, performance, and cost tradeoffs ... Mechanical Engineering, or Material Sciences disciplines. 6+ months of experience with the ...
Silicon Packaging Design Engineer
Phoenix, AZ · On-site
$105.65K - $149.15K/yr
Perform substrate fit and routing studies to establish design, performance, and cost tradeoffs ... Mechanical Engineering, or Material Sciences disciplines. 6+ months of experience with the ...
Silicon Packaging Design Engineer
Phoenix, AZ · On-site
$105.65K - $149.15K/yr
Perform substrate fit and routing studies to establish design, performance, and cost tradeoffs ... Mechanical Engineering, or Material Sciences disciplines. 6+ months of experience with the ...
Silicon Packaging Design Engineer
Phoenix, AZ · On-site
$105.65K - $149.15K/yr
Perform substrate fit and routing studies to establish design, performance, and cost tradeoffs ... Mechanical Engineering, or Material Sciences disciplines. 6+ months of experience with the ...
Lead package material selection, substrate stack-up definition, mechanical modeling, and ... Deep knowledge of Electrical Engineering concepts, circuit extractions and simulation, as well as ...
Lead package material selection, substrate stack-up definition, mechanical modeling, and ... Deep knowledge of Electrical Engineering concepts, circuit extractions and simulation, as well as ...
Lead package material selection, substrate stack-up definition, mechanical modeling, and ... Deep knowledge of Electrical Engineering concepts, circuit extractions and simulation, as well as ...
Lead package material selection, substrate stack-up definition, mechanical modeling, and ... Deep knowledge of Electrical Engineering concepts, circuit extractions and simulation, as well as ...
Lead package material selection, substrate stack-up definition, mechanical modeling, and ... Bachelor's degree in Mechanical Engineering, Material Science, Electrical Engineering or related ...
Lead package material selection, substrate stack-up definition, mechanical modeling, and ... Bachelor's degree in Mechanical Engineering, Material Science, Electrical Engineering or related ...
Lead package material selection, substrate stack-up definition, mechanical modeling, and ... Deep knowledge of Electrical Engineering concepts, circuit extractions and simulation, as well as ...
Lead package material selection, substrate stack-up definition, mechanical modeling, and ... Deep knowledge of Electrical Engineering concepts, circuit extractions and simulation, as well as ...
Lead package material selection, substrate stack-up definition, mechanical modeling, and ... Bachelor's degree in Mechanical Engineering, Material Science, Electrical Engineering or related ...
Lead package material selection, substrate stack-up definition, mechanical modeling, and ... Bachelor's degree in Mechanical Engineering, Material Science, Electrical Engineering or related ...
Yield Engineer On Shift
Phoenix, AZ · On-site
$85.20K - $139.81K/yr
Join Intel's Advanced Packaging Team as part of the Substrate Packaging Technology Development ... Yield Engineer On Shift (YEOS): As a YEOS engineer, you will provide critical factory support by ...
Yield Engineer On Shift
Phoenix, AZ · On-site
$85.20K - $139.81K/yr
Join Intel's Advanced Packaging Team as part of the Substrate Packaging Technology Development ... Yield Engineer On Shift (YEOS): As a YEOS engineer, you will provide critical factory support by ...
Yield Engineer On Shift
$81.10K - $114.60K/yr
Join Intel's Advanced Packaging Team as part of the Substrate Packaging Technology Development ... Yield Engineer On Shift (YEOS): As a YEOS engineer, you will provide critical factory support by ...
Yield Engineer On Shift
$81.10K - $114.60K/yr
Join Intel's Advanced Packaging Team as part of the Substrate Packaging Technology Development ... Yield Engineer On Shift (YEOS): As a YEOS engineer, you will provide critical factory support by ...
Yield Engineer On Shift
$85.20K - $139.81K/yr
Join Intel's Advanced Packaging Team as part of the Substrate Packaging Technology Development ... Yield Engineer On Shift (YEOS): As a YEOS engineer, you will provide critical factory support by ...
Yield Engineer On Shift
$85.20K - $139.81K/yr
Join Intel's Advanced Packaging Team as part of the Substrate Packaging Technology Development ... Yield Engineer On Shift (YEOS): As a YEOS engineer, you will provide critical factory support by ...
Job Details: This is an exciting opportunity to join the Substrate Business Group which ... Apply technical/engineering background to create and communicate accurate capability and capacity ...
Job Details: This is an exciting opportunity to join the Substrate Business Group which ... Apply technical/engineering background to create and communicate accurate capability and capacity ...
Substrate Engineer information
What are the key skills and qualifications needed to thrive as a Substrate Engineer, and why are they important?
What are some common challenges Substrate Engineers face when working on high-density interconnect (HDI) designs?
What is a Substrate Engineer?
What jobs make $3,000 a month without a degree?
What is the difference between Substrate Engineer vs Semiconductor Process Engineer?
| Aspect | Substrate Engineer | Semiconductor Process Engineer |
|---|---|---|
| Credentials | Bachelor's or Master's in Materials Science, Electrical Engineering, or related fields | Bachelor's or Master's in Electrical Engineering, Chemical Engineering, or related fields |
| Work Environment | Research labs, fabrication facilities, semiconductor manufacturing plants | Cleanrooms, fabrication facilities, process development labs |
| Industry Usage | Semiconductor manufacturing, electronics, integrated circuits | Semiconductor fabrication, chip production, process optimization |
| Common Search/Comparison | Yes | Yes |
Substrate Engineers focus on developing and optimizing the materials and layers used in semiconductor devices, while Semiconductor Process Engineers work on the overall manufacturing processes to produce chips efficiently. Both roles require similar educational backgrounds and often collaborate within the semiconductor industry, but their specific responsibilities differ in scope and focus.
Full-time
Medical, Retirement, PTO
Posted 21 days ago
Intel rating
8.8
Based on 143 frontline employees who took The Breakroom Quiz
9th of 137 rated electronics manufacturers
Job description
Job Description:
The Advanced Packaging Technology Development (APTD) Substrate and Wafer Assembly organization is responsible for developing cutting edge substrate packaging and wafer assembly solutions for our customers. As a member of the Substrate Technology Integration Group, you will play a critical role in enabling new manufacturing capacity across advanced packaging suppliers.
In this position, you will lead substrate supplier development and qualification activities, ensuring suppliers achieve the required readiness to support growing customer demand. This includes driving technical enablement, managing readiness milestones, and collaborating closely with cross functional engineering teams and supplier partners.
Please note: This role requires periodic evening meetings with suppliers in East Asia, as well as occasional travel to supplier sites to support essential program objectives.
Responsibilities
• Collaborate with suppliers and internal engineering teams to develop robust building block processes across component embedding, core fabrication, laser drilling, dielectric lamination, lithography, electrolytic multi metal plating, defect inspection/metrology, electrical testing, and other substrate technologies.
• Partner closely with on site supplier engineering teams and the APTD Substrate Integration team to advance substrate building block technologies and manage critical process interactions.
• Ensure suppliers meet all Product Control System (PCS) commitments with rigor and consistency.
• Work with cross functional teams to design and implement new factory technology validation and product certification plans focused on yield improvement.
• Develop and maintain detailed micro schedules for new factory startup activities, including key milestones, to ensure supplier alignment with startup timelines.
• Lead qualification activities and monitor ramp indicators to enable an incident free production ramp and successful introduction of new capacity.
Behavioral traits:
- Proactive and adaptable approach to challenges, with the ability to excel under pressure.
- Strong collaboration, communication, and leadership skills to drive cross-functional initiatives.
- Enthusiasm for learning and contributing to Intel's mission of technology leadership.
Qualifications:
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.
Minimum Qualifications
- Bachelor's degree with 6+ years of experience, OR Master's degree with 4+ years of experience, OR PhD with 2+ years of experience in Mechanical Engineering, Materials Science, Chemical Engineering, Electrical Engineering, Physics, or a related technical field.
Experience listed above should be in the following:
- Statistical tools and methods, including Statistical Process Control (SPC) for yield improvement. .
- Experience managing complex projects and deliver results in high-volume manufacturing environments.
Preferred Qualifications
- A strong foundation in advanced packaging, substrates, or semiconductor manufacturing; proven leadership in supplier management or technology enablement; and the ability to drive alignment and execution across global teams.
- Proven ability to thrive in high-ambiguity environments and deliver results under pressure. Knowledge of advanced packaging technologies and substrate/assembly manufacturing methodologies.
- Familiarity with characterization techniques such as X-ray, SEM, FTIR, and EDX.
- Experience with process flow development, FMEA, DOE design, and problem-solving tools.
Make your mark by applying today and be part of shaping the future of innovation at Intel.
Job Type:
Experienced Hire
Shift:
Shift 1 (United States of America)
Primary Location:
US, Arizona, Phoenix
Additional Locations:
Business group:
Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while delighting our customers -- from delivering cutting-edge silicon process and packaging technology leadership for the AI era, enabling our customers to design leadership products, global manufacturing scale and supply chain, through the continuous yield improvements to advanced packaging all the way to final test and assembly. We ensure our foundry customers' products receive our utmost focus in terms of service, technology enablement and capacity commitments. Employees in the Foundry Technology Manufacturing are part of a worldwide factory network that designs, develops, manufactures, and assembly/test packages the compute devices to improve the lives of every person on Earth.
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $120,860.00-231,670.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
About Intel
Sourced by ZipRecruiter
Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth
Industry
Manufacturing
Company size
10,000+ Employees
Headquarters location
Santa Clara, CA, US
Year founded
1968