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Silicon Package Design Engineer Jobs (NOW HIRING)

Senior Package Design Engineer

San Jose, CA ยท Hybrid

$110K - $205K/yr

Rambus, a premier chip and silicon IP provider making data faster and safer, is seeking to hire an exceptional Senior Package Design Engineer to join our Package Engineering team in San Jose, CA. In ...

Senior Package Design Engineer

San Jose, CA ยท On-site

$110K - $205K/yr

Overview Rambus, a premier chip and silicon IP provider making data faster and safer, is seeking to hire an exceptional Senior Package Design Engineer to join our Package Engineering team in San Jose ...

Scope all aspects of package design feasibility at Silicon interposer and substrate level for multi-chip SiP packaging. * Support pre/post silicon bring up, yield improvement activities ...

As a Senior Package Design Engineer, you will lead co-design activities that bridge silicon design, package architecture, and product development for advanced DRAM and memory products targeting ...

Senior Package Design Engineer

San Jose, CA ยท Hybrid

$110K - $205K/yr

Overview Rambus, a premier chip and silicon IP provider making data faster and safer, is seeking to hire an exceptional Senior Package Design Engineer to join our Package Engineering team in San Jose ...

High-Speed Package Design Engineer

Murray Hill, NJ ยท On-site

$143K/yr

Nokia Bell Labs is seeking a High-Speed Package Design Engineer to drive the design, simulation ... silicon, PCB, and system integration teams. The successful candidate will also contribute to ...

Scope all aspects of package design feasibility at Silicon interposer and substrate level for multi-chip SiP packaging. * Support pre/post silicon bring up, yield improvement activities ...

OR

$200K - $280K/yr

Partner with silicon, RF, and systems teams to co-optimize die floorplans and package interfaces ... Engineering, or a related field. * 10+ years of experience in ASIC package design, with deep ...

Partner with silicon, RF, and systems teams to co-optimize die floorplans and package interfaces ... Engineering, or a related field. * 10+ years of experience in ASIC package design, with deep ...

OR ยท On-site

$180K - $260K/yr

Partner with silicon, RF, and systems teams to co-optimize die floorplans and package interfaces ... Engineering, or a related field. * 5+ years of experience in ASIC package design, with deep ...

Package Design Engineer

Austin, TX ยท On-site

$141K - $226K/yr

Broadcom is seeking an experienced IC package-design engineer for complex flip-chip-BGA packages for industry-leading ASICs with high-speed SerDes and very-high-power delivery needs. You will be part ...

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Silicon Package Design Engineer information

See salary details

$90K

$136.5K

How much do silicon package design engineer jobs pay per year?

As of Jun 8, 2026, the average yearly pay for silicon package design engineer in the United States is $135,040.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $136,000.00 per year, depending on experience, location, and employer.

What is the difference between Silicon Package Design Engineer vs PCB Design Engineer?

AspectSilicon Package Design EngineerPCB Design Engineer
CredentialsBachelor's or Master's in Electrical Engineering, VLSI, or related fieldsBachelor's or Master's in Electrical Engineering, Electronics, or related fields
Work EnvironmentSemiconductor fabrication labs, design houses, R&D centersElectronics manufacturing, design firms, product development teams
Industry UsageSemiconductor industry, integrated circuit designConsumer electronics, industrial equipment, communication devices
Primary FocusDesigning silicon chip packages, ensuring electrical and thermal performanceDesigning printed circuit boards for electronic products

The Silicon Package Design Engineer focuses on creating and optimizing the packaging of silicon chips, ensuring electrical connectivity and thermal management. In contrast, the PCB Design Engineer specializes in designing printed circuit boards that connect various electronic components. While both roles require electrical engineering knowledge, their work environments and end products differ significantly.

What types of cross-functional teams do Silicon Package Design Engineers typically collaborate with, and how does this affect daily workflow?

Silicon Package Design Engineers often work closely with electrical engineers, mechanical engineers, manufacturing teams, and product managers to ensure package designs meet performance, reliability, and manufacturability standards. This collaborative environment means that daily tasks often involve design reviews, resolving integration challenges, and coordinating updates based on feedback from various disciplines. Effective communication and teamwork are essential, as design changes in one area can significantly impact other aspects of the product. This cross-functional dynamic offers valuable insight into the entire product development lifecycle and fosters broad technical growth.

What does a Silicon Package Design Engineer do?

A Silicon Package Design Engineer is responsible for designing the physical packaging that houses silicon chips, ensuring optimal electrical performance, thermal management, and mechanical integrity. They collaborate with cross-functional teams to develop package layouts, select materials, and address challenges related to signal integrity, power distribution, and manufacturability. Their work is crucial for protecting the silicon die and enabling reliable integration into electronic devices. This role often involves using specialized design software and working closely with fabrication and testing teams to deliver high-quality, cost-effective packaging solutions.

What are the key skills and qualifications needed to thrive as a Silicon Package Design Engineer, and why are they important?

To thrive as a Silicon Package Design Engineer, you need a solid background in electrical or materials engineering, semiconductor packaging principles, and experience with design for manufacturability. Proficiency in industry-standard EDA tools such as Cadence, Mentor Graphics, or Ansys, along with familiarity with simulation and layout software, is typically required. Strong problem-solving skills, attention to detail, and effective communication are critical for collaborating with multidisciplinary teams and resolving design challenges. These skills and qualifications are essential for delivering reliable, high-performance semiconductor packages that meet stringent industry standards.
More about Silicon Package Design Engineer jobs
Senior Package Design Engineer

Senior Package Design Engineer

Rambus

San Jose, CA โ€ข Hybrid

$110K - $205K/yr

Full-time

Medical, Dental, Retirement

Posted 12 days ago


Job description

Rambus, a premier chip and silicon IP provider making data faster and safer, is seeking to hire an exceptional Senior Package Design Engineer to join our Package Engineering team in San Jose, CA. In this role, you will be working with some of the brightest inventors and engineers in the world developing products that make data faster and safer.

This is a full-time position reporting to the Director of Package Engineering. As a Senior Package Design Engineer, you will be responsible for supporting the design and layout of new products from early concept to tape out, focusing primarily on several elements that enable high-yielding, low defectivity production. The Senior Package Design Engineer will have the opportunity to work with multiple package technologies and outsourced suppliers to ensure manufacturing readiness for the Rambus product portfolio.

Rambus offers a flexible work environment, embracing a hybrid approach for most office-based roles. Employees are encouraged to spend an average of at least three days per week onsite, allowing for two days of remote work.


  • Drive early chip-package co-design and development of bump and ball map.
  • Own layout of package types such as FCCSP, FCBGA, FCQFN, WLCSP, QFN.
  • Collaborate with multiple cross-functional teams (Chip Design, SI/PI, Packaging)
  • Analyze cost/performance/reliability trade-offs to complete layout of new products and test chips.
  • Interact with OSAT partners and substrate/leadframe suppliers for design reviews and execution.
  • Continuous improvement of package design workflow and unified package design guidelines.
  • Assist with model creation for thermo-mechanical package simulations.

  • MS Degree in EE/CE
  • Proficiency with Cadence Allegro Package Designer (APD) and AutoCAD.
  • 5+ years of experience in packaging design and layout, preferably in an advanced silicon node.
  • Proven track record with multiple packaging types where products have gone to volume production.
  • Experience routing high-speed, high pin count devices and understanding of signal and power integrity fundamentals.
  • Knowledge of organic laminate substrate technologies and manufacturing capabilities.
  • Awareness of JEDEC standards and other specifications that may govern package design.
  • Understanding of package material properties related to high-volume production and reliability: temperature cycling, HAST, shock, vibration, thermal resistance, outgassing, etc.
  • Excellent communication, initiative, multi-tasking, and time management.
  • Strong commitment and ability to work in cross functional and globally dispersed teams

About Rambusย 

Rambus is a global company that makes industry-leading memory interface chips and Silicon IP to advance data center connectivity and solve the bottleneck between memory and processing. With over 30 years of semiconductor experience, we are a leading provider of high-performance products and innovations that maximize the bandwidth, capacity and security for AI and other data-intensive workloads. Our world-class team is the foundation of our company, and our innovative spirit drives us to develop theย cutting-edgeย products and technologies essential for tomorrowโ€™s systems.ย ย 

Rambus offers a competitive compensation packageย includingย base salary, bonus, equity, matching 401(k), employee stock purchase plan, comprehensive medical and dental benefits, time-off program, and gym membership.ย ย 

Theย USย salary range for thisย full-timeย position is $110,700ย to $205,700.ย Our salary ranges areย determinedย by role,ย levelย and location. The successful candidateโ€™s starting pay will beย determinedย based on job-related skills, experience, qualifications, workย locationย and market conditions.ย 

At Rambus, we are committed to fostering a workplace where every individual is respected, supported, and empowered to succeed. We value a range of perspectives and experiences that contribute to innovation and collaboration. Our goal is to ensure that all team members haveย equitableย access to opportunities, resources, and a sense of belonging. We believe that a culture of fairness and inclusion helps us all do ourย best work.ย 

ย 
Rambus is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, or other applicable legally protected characteristics.ย ย 

Rambus is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veteransย duringย our job application procedures. If youย requireย assistanceย orย an accommodationย due to a disability,ย please feel free to inform us in your application.ย 

Rambus does not accept unsolicited resumes from headhunters, recruitmentย agenciesย or fee-based recruitment services.ย 

For more information about Rambus, visit rambus.com. Forย additionalย information on life at Rambus and our current openings, check outrambus.com/careers/.ย 

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