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Silicon Package Design Engineer Jobs (NOW HIRING)

Intel

Silicon Packaging Design Engineer

Phoenix, AZ · On-site

$105K - $149K/yr

As a Silicon Packaging Design Engineer, you will play a pivotal role in driving the development of ... Drive the physical layout and routing of package designs, ensuring alignment with silicon, package ...

Intel

Silicon Packaging Design Engineer

Phoenix, AZ · On-site

$135K/yr

Job Details: We are seeking an experienced Silicon Packaging Design Engineer with a strong ... Partner closely with package design, test engineering, and validation teams to define board ...

Intel

Silicon Packaging Design Engineer

Hillsboro, OR · On-site

$148K/yr

Job Details: We are seeking an experienced Silicon Packaging Design Engineer with a strong ... Partner closely with package design, test engineering, and validation teams to define board ...

Apple Inc.

IC Package Design Engineer

Austin, TX · On-site

$90 - $130/hr

Description As a Package design engineer, you will lead advanced package architecture, drive ... Perform physical layout of package substrates for diverse silicon, including System‑on‑Chip ...

Lightmatter

Package Layout Engineer

Mountain View, CA · Hybrid

About This Role Lightmatter is looking for a Package Layout Design Engineer to drive the next ... Silicon/package/MB) optimization. * Collaborate with package substrate suppliers and Outsourced ...

Intel

Silicon Packaging Design Engineer

Phoenix, AZ · On-site

$135K/yr

Intel seeks a motivated and innovative Silicon Packaging Design Engineer to join our team, driving ... package performance, and delivering high-impact solutions that meet performance, cost, and ...

Apple

IC Package Design Engineer

Austin, TX

$175K - $308K/yr

Description As a Package design engineer, you will lead advanced package architecture, drive next ... wide range of silicon technologies You are expected to leverage AI tools to enhance design ...

Apple

IC Package Design Engineer

Los Angeles, CA

$122K - $214K/yr

Description As a Package design engineer, you will lead advanced package architecture, drive next ... wide range of silicon technologies You are expected to leverage AI tools to enhance design ...

Intel

Silicon Packaging Design Engineer

Hillsboro, OR · On-site

$148K/yr

Intel seeks a motivated and innovative Silicon Packaging Design Engineer to join our team, driving ... package performance, and delivering high-impact solutions that meet performance, cost, and ...

Apple

IC Package Design Engineer

Austin, TX

$175K - $308K/yr

Description As a Package design engineer, you will lead advanced package architecture, drive next ... wide range of silicon technologies You are expected to leverage AI tools to enhance design ...

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Silicon Package Design Engineer information

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$90K

$136.5K

How much do silicon package design engineer jobs pay per year?

As of Sep 2, 2026, the average yearly pay for silicon package design engineer in the United States is $135,040.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $136,000.00 per year, depending on experience, location, and employer.

What does a silicon package design engineer do?

A Silicon Package Design Engineer is responsible for designing the physical packaging that houses silicon chips, ensuring optimal electrical performance, thermal management, and mechanical integrity. They collaborate with cross-functional teams to develop package layouts, select materials, and address challenges related to signal integrity, power distribution, and manufacturability. Their work is crucial for protecting the silicon die and enabling reliable integration into electronic devices. This role often involves using specialized design software and working closely with fabrication and testing teams to deliver high-quality, cost-effective packaging solutions.

What skills and qualifications are needed to thrive as a silicon package design engineer?

To thrive as a Silicon Package Design Engineer, you need a solid background in electrical or materials engineering, semiconductor packaging principles, and experience with design for manufacturability. Proficiency in industry-standard EDA tools such as Cadence, Mentor Graphics, or Ansys, along with familiarity with simulation and layout software, is typically required. Strong problem-solving skills, attention to detail, and effective communication are critical for collaborating with multidisciplinary teams and resolving design challenges. These skills and qualifications are essential for delivering reliable, high-performance semiconductor packages that meet stringent industry standards.

What types of cross-functional teams do silicon package design engineers typically collaborate with, and how does this affect daily workflow?

Silicon Package Design Engineers often work closely with electrical engineers, mechanical engineers, manufacturing teams, and product managers to ensure package designs meet performance, reliability, and manufacturability standards. This collaborative environment means that daily tasks often involve design reviews, resolving integration challenges, and coordinating updates based on feedback from various disciplines. Effective communication and teamwork are essential, as design changes in one area can significantly impact other aspects of the product. This cross-functional dynamic offers valuable insight into the entire product development lifecycle and fosters broad technical growth.

What is the difference between Silicon Package Design Engineer vs PCB Design Engineer?

AspectSilicon Package Design EngineerPCB Design Engineer
CredentialsBachelor's or Master's in Electrical Engineering, VLSI, or related fieldsBachelor's or Master's in Electrical Engineering, Electronics, or related fields
Work EnvironmentSemiconductor fabrication labs, design houses, R&D centersElectronics manufacturing, design firms, product development teams
Industry UsageSemiconductor industry, integrated circuit designConsumer electronics, industrial equipment, communication devices
Primary FocusDesigning silicon chip packages, ensuring electrical and thermal performanceDesigning printed circuit boards for electronic products

The Silicon Package Design Engineer focuses on creating and optimizing the packaging of silicon chips, ensuring electrical connectivity and thermal management. In contrast, the PCB Design Engineer specializes in designing printed circuit boards that connect various electronic components. While both roles require electrical engineering knowledge, their work environments and end products differ significantly.

More about Silicon Package Design Engineer jobs

What job categories do people searching Silicon Package Design Engineer jobs look for?

The top searched job categories for Silicon Package Design Engineer jobs are:

Silicon Package Design Engineer jobs near you
Infographic showing various Silicon Package Design Engineer job openings in the United States as of August 2026, with employment types broken down into 76% Full Time, 11% Part Time, and 13% Contract. Highlights an 85% Physical, 2% Hybrid, and 13% Remote job distribution, with an average salary of $135,040 per year, or $64.9 per hour.

Silicon Packaging Design Engineer

Intel

Phoenix, AZ • On-site

$105K - $149K/yr

Full-time

Medical, Retirement, PTO

Re-posted 9 days ago

Intel rating

8.7

Company rating: 8.7 out of 10

Based on 147 frontline employees who took The Breakroom Quiz

18th of 160 rated electronics manufacturers

Job description

Job Details:Job Description: 

As a Silicon Packaging Design Engineer, you will play a pivotal role in driving the development of advanced substrate designs, contributing to the creation of cutting-edge technology that fuels Intel's innovation. You will be responsible for the end-to-end development of substrate designs, from concept through tape-out, ensuring optimal performance, cost efficiency, and manufacturability. This position provides an exciting opportunity to work collaboratively with silicon and hardware teams, directly impacting Intel's success in delivering world-class solutions for high-performance applications.

Key Responsibilities

  • Drive the physical layout and routing of package designs, ensuring alignment with silicon, package, and board performance requirements.
  • Perform substrate fit and routing studies to establish design, performance, and cost tradeoffs.
  • Define and implement substrate design rules, conducting internal and external reviews to ensure designs meet quality standards.
  • Analyze data, resolve Design Rule Checks (DRCs), and optimize package designs for manufacturability and performance.
  • Collaborate with cross-functional teams to optimize pinout and silicon-package-board interactions.
  • Complete documentation and collateral into the product lifecycle management system of record

Behavioral traits

  • Problem-solving skills and a proactive approach to challenges.
  • Excellent communication and interpersonal skills for effective cross-functional collaboration.
  • Manage multiple tasks and projects simultaneously under tight deadlines.
Qualifications:

Minimum qualifications are required to be initially considered for this position.

Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. This position is not eligible for Intel immigration sponsorship

Knowledge and/or experience listed below would be obtained through a combination of your school/work and/or classes and/or research and/or relevant previous job and/or internship experiences.

Minimum Qualifications

  • Bachelors with 1+ years of experience or master's degree with 6 months of experience in Electrical Engineering, Mechanical Engineering, or Material Sciences disciplines.
  • 6+ months of experience with the following technical skills:
    • Experience and/or familiarity with microelectronic package or PCB physical layout design and manufacturing process.
    • Familiarity with package design tools like Siemens Xpedition, Cadence Allegro Package Design, AutoCAD, or SolidWorks.
    • Familiarity with physical layout aspects of substrate design, including custom layouts, floor plans, or schematic layout conversion.

Preferred Qualifications:

  • Experience in microelectronic package substrate design, package I/O routing, and/or technology development.
  • Familiarity with microelectronic package electrical modeling and simulation tools such as PowerDC, HyperLynx, Q3D, and HFSS.
  • Experience with package design tools such as Package Layout Automation (PLA) and FIELD.
  • Experience with scripting using Python, VB, C, or similar languages
Job Type:College GradShift:Shift 1 (United States of America)Primary Location: US, Arizona, PhoenixAdditional Locations:Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $105,650.00-149,150.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

*

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

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About Intel

Sourced by ZipRecruiter

Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth

Industry

Manufacturing

Company size

10,000+ Employees

Headquarters location

Santa Clara, CA, US

Year founded

1968

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