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Senior Ic Layout Design Engineer Jobs (NOW HIRING)

Nvidia

Senior SRAM Layout Design Engineer

Durham, NC · Hybrid

Are you looking for a Mask layout Design Engineer role? We are seeking a hands-on Senior SRAM ... What we need to see: * Have a BSEE or equivalent experience * 10+ years of custom IC layout ...

SRI International

Analog IC Design Engineer

Princeton, NJ · On-site

$104K - $137K/yr

... with senior designers, define architecture, design and model circuit components for optimal ... Experience in analog IC layout to address DRC, LVS, matching, shielding, electromigration, IR drops ...

Analog Devices

Lead Analog IC Layout Engineer

Wilmington, MA · On-site

$134K - $201K/yr

As a Lead Designer, Layout, you hold a senior technical position working on our most complex layout ... Makes critical IC architecture design decisions that shape product development * Performs advanced ...

Nvidia

Senior SRAM Layout Design Engineer

Austin, TX · Hybrid

Are you looking for a Mask layout Design Engineer role? We are seeking a hands-on Senior SRAM ... What we need to see: * Have a BSEE or equivalent experience * 10+ years of custom IC layout ...

SRI International

Analog IC Design Engineer

Princeton, NJ · On-site

$104K - $137K/yr

... with senior designers, define architecture, design and model circuit components for optimal ... Experience in analog IC layout to address DRC, LVS, matching, shielding, electromigration, IR drops ...

Analogdevices

$134K - $201K/yr

As a Lead Designer, Layout, you hold a senior technical position working on our most complex layout ... Makes critical IC architecture design decisions that shape product development * Performs advanced ...

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Senior Ic Layout Design Engineer information

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$63K

$121.5K

$191.5K

How much do senior ic layout design engineer jobs pay per year?

As of Jul 12, 2026, the average yearly pay for senior ic layout design engineer in the United States is $121,466.00, according to ZipRecruiter salary data. Most workers in this role earn between $95,000.00 and $138,500.00 per year, depending on experience, location, and employer.

What does a Senior IC Layout Design Engineer do?

A Senior IC Layout Design Engineer is responsible for designing the physical layout of integrated circuits (ICs) based on schematic diagrams and electrical requirements. They use specialized software tools to arrange transistors, resistors, and other components on a silicon chip, ensuring optimal performance, manufacturability, and adherence to design rules. In addition, they often lead layout projects, review the work of junior engineers, and collaborate closely with circuit designers and verification teams to meet technical specifications and project deadlines.

What are the key skills and qualifications needed to thrive as a Senior IC Layout Design Engineer, and why are they important?

A Senior IC Layout Design Engineer requires expertise in analog and digital layout design, semiconductor device physics, and a relevant engineering degree, often with several years of industry experience. Proficiency in EDA tools such as Cadence Virtuoso, Mentor Graphics, and knowledge of DRC/LVS verification flows are typically expected. Attention to detail, problem-solving abilities, and effective communication are crucial soft skills for collaborating with cross-functional teams and ensuring design accuracy. These skills and qualifications are essential for creating high-performance, reliable integrated circuits that meet stringent specifications and industry standards.

What are some common challenges Senior IC Layout Design Engineers face when collaborating with cross-functional teams?

Senior IC Layout Design Engineers often work closely with circuit designers, verification engineers, and process engineers. A common challenge is ensuring that layout constraints align with the circuit’s performance requirements while also meeting manufacturing design rules and timelines. Effective communication and quick resolution of conflicting priorities are crucial, as design iterations can be frequent. Developing strong collaborative relationships and maintaining detailed documentation can help overcome these challenges and lead to successful project outcomes.
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Senior Ic Layout Design Engineer jobs near you
Infographic showing various Senior Ic Layout Design Engineer job openings in the United States as of July 2026, with employment types broken down into 89% Full Time, 8% Part Time, and 3% Contract. Highlights an 87% Physical, 3% Hybrid, and 10% Remote job distribution, with an average salary of $121,466 per year, or $58.4 per hour.
Senior High Speed Mixed-Signal I/O & Analog Layout Engineer

Senior High Speed Mixed-Signal I/O & Analog Layout Engineer

West Coast Consulting

San Jose, CA • On-site

$105 - $110/hr

Other

Posted 9 days ago

Job description

Job Description Onsite in San Jose, CA 5 days a week Description As a senior high speed mixed-signal layout/analog layout engineer, you will be working with circuit designers located in San Jose, California, USA to accomplish layout tasks. Circuits that you will need to work on includes High Speed RX (receiver), TX (transmitters), PLL, CDR, Analog reference circuits, and so on. You should have experiences doing layout with sub-micron CMOS technologies, Responsibilities: Working with remote circuit designers to determine the chip floorplan.

You need to come up with strategies to optimize the parasites, reduce area, and improve High Speed SERDES/analog performance. You need to be able to estimate schedule and come up with plan how to get things done within a dedicated time frame. You should be able to read the design document provided by the foundry and figure out how to resolve issues like latch-up and DRC.

Perform custom layout using Virtuoso, and be able to get LVS/DRC clean. You should be familiar with CAD tools, including Virtuoso, Calibre LVS, DRC, SkillCad and so on. Desired to have experience on chip level design, like bump, pad, and ESD strategies.

Good communication skills to discuss with circuit designer. Requirements: Bachelor s degree in electrical or computer engineering and 5+ years of professional experience as an IC layout designer; OR 8+ years of professional experience with integrated circuit layout design in lieu of a degree Preferred Skills: Strong High Speed SERDES/analog layout skills Experience in advanced nodes in IC layout, including finfet 14nm, 8nm, 4nm and 2nm GAA. Experience in IC layouts with frequencies up to 224Gb/s.

Experience in critical IC layouts, including VCO, clocking circuit, TX, and RX and so on. Working knowledge in Linux Proficiency in CAD tools including Cadence Virtuoso, Calibre LVS, DRC, and SkillCad. Excellency in communications skills in the form of verbal, email, and in documentations.

Be able to work independently. Good to have experience to lead a small team and tape-out an analog IC.

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