Miami, FL · On-site
$4.3K - $4.8K/wk
Experienced in RTL Design (SystemVerilog preferred). Python, C, Tcl, and Bash a plus. * Experience in one or more of the following areas: Hardware Architecture, Simulation, Systems Integration ...
Miami, FL · On-site
$4.3K - $4.8K/wk
Experienced in RTL Design (SystemVerilog preferred). Python, C, Tcl, and Bash a plus. * Experience in one or more of the following areas: Hardware Architecture, Simulation, Systems Integration ...
RTL Design & Simulation: Develop code and testbenches using VHDL, Verilog, and SystemVerilog. * Verification: Create UVM constrained random environments and conduct static timing, linting, and clock ...
Quick apply
RTL Design & Simulation: Develop code and testbenches using VHDL, Verilog, and SystemVerilog. * Verification: Create UVM constrained random environments and conduct static timing, linting, and clock ...
Melbourne, FL · On-site
$114K - $151K/yr
RTL Design & Simulation: Develop code and testbenches using VHDL, Verilog, and SystemVerilog. * Verification: Create UVM constrained random environments and conduct static timing, linting, and clock ...
Quick apply
Melbourne, FL · On-site
$114K - $151K/yr
RTL Design & Simulation: Develop code and testbenches using VHDL, Verilog, and SystemVerilog. * Verification: Create UVM constrained random environments and conduct static timing, linting, and clock ...
RTL Design & Simulation: Develop code and testbenches using VHDL, Verilog, and SystemVerilog. * Verification: Create UVM constrained random environments and conduct static timing, linting, and clock ...
Quick apply
RTL Design & Simulation: Develop code and testbenches using VHDL, Verilog, and SystemVerilog. * Verification: Create UVM constrained random environments and conduct static timing, linting, and clock ...
Core Responsibilities RTL Design & Simulation: Develop code and testbenches using VHDL, Verilog, and SystemVerilog. Verification: Create UVM constrained random environments and conduct static timing ...
Core Responsibilities RTL Design & Simulation: Develop code and testbenches using VHDL, Verilog, and SystemVerilog. Verification: Create UVM constrained random environments and conduct static timing ...
Melbourne, FL · On-site
$114K - $157K/yr
Develop RTL design code and simulation in VHDL, Verilog, and/or SystemVerilog. * Create testcases and test procedures for verification environments using SystemVerilog or VHDL * Create placement and ...
Melbourne, FL · On-site
$114K - $157K/yr
Develop RTL design code and simulation in VHDL, Verilog, and/or SystemVerilog. * Create testcases and test procedures for verification environments using SystemVerilog or VHDL * Create placement and ...
RTL Design & Simulation: Develop code and testbenches using VHDL, Verilog, and SystemVerilog. * Verification: Create UVM constrained random environments and conduct static timing, linting, and clock ...
Quick apply
RTL Design & Simulation: Develop code and testbenches using VHDL, Verilog, and SystemVerilog. * Verification: Create UVM constrained random environments and conduct static timing, linting, and clock ...
$114K - $157K/yr
Develop RTL design code and simulation in VHDL, Verilog, and/or SystemVerilog. * Create testcases and test procedures for verification environments using SystemVerilog or VHDL * Create placement and ...
$114K - $157K/yr
Develop RTL design code and simulation in VHDL, Verilog, and/or SystemVerilog. * Create testcases and test procedures for verification environments using SystemVerilog or VHDL * Create placement and ...
Melbourne, FL · On-site
$114K - $151K/yr
RTL Design & Simulation: Develop code and testbenches using VHDL, Verilog, and SystemVerilog. * Verification: Create UVM constrained random environments and conduct static timing, linting, and clock ...
Quick apply
Melbourne, FL · On-site
$114K - $151K/yr
RTL Design & Simulation: Develop code and testbenches using VHDL, Verilog, and SystemVerilog. * Verification: Create UVM constrained random environments and conduct static timing, linting, and clock ...
Orlando, FL · On-site
$127K - $155K/yr
In this role, you'll be responsible for block and sub-system level pre-silicon RTL verification of ... design specification. - Develop and drive verification plans and schedules. - Architect test ...
Orlando, FL · On-site
$127K - $155K/yr
In this role, you'll be responsible for block and sub-system level pre-silicon RTL verification of ... design specification. - Develop and drive verification plans and schedules. - Architect test ...
$127K - $155K/yr
In this role, you'll be responsible for block and sub-system level pre-silicon RTL verification of ... design specification. - Develop and drive verification plans and schedules. - Architect test ...
$127K - $155K/yr
In this role, you'll be responsible for block and sub-system level pre-silicon RTL verification of ... design specification. - Develop and drive verification plans and schedules. - Architect test ...
Orlando, FL · On-site
$127K - $155K/yr
You'll be responsible for block and sub-system level pre-silicon RTL verification. You will also ... Experience or coursework in digital design/verification. Experience or coursework with object ...
Orlando, FL · On-site
$127K - $155K/yr
You'll be responsible for block and sub-system level pre-silicon RTL verification. You will also ... Experience or coursework in digital design/verification. Experience or coursework with object ...
$127K - $155K/yr
You'll be responsible for block and sub-system level pre-silicon RTL verification. You will also ... Experience or coursework in digital design/verification. Experience or coursework with object ...
$127K - $155K/yr
You'll be responsible for block and sub-system level pre-silicon RTL verification. You will also ... Experience or coursework in digital design/verification. Experience or coursework with object ...
Melbourne, FL · On-site
You will closely interact with RTL designer to understand design intent and clock structure, with CAD to understand and develop flow, and with Physical design team to close and sign-off timing. You ...
Melbourne, FL · On-site
You will closely interact with RTL designer to understand design intent and clock structure, with CAD to understand and develop flow, and with Physical design team to close and sign-off timing. You ...
Melbourne, FL · On-site
You will closely interact with RTL designer to understand design intent and clock structure, with CAD to understand and develop flow, and with Physical design team to close and sign-off timing. You ...
Melbourne, FL · On-site
You will closely interact with RTL designer to understand design intent and clock structure, with CAD to understand and develop flow, and with Physical design team to close and sign-off timing. You ...
You will closely interact with RTL designer to understand design intent and clock structure, with CAD to understand and develop flow, and with Physical design team to close and sign-off timing. You ...
You will closely interact with RTL designer to understand design intent and clock structure, with CAD to understand and develop flow, and with Physical design team to close and sign-off timing. You ...
You will closely interact with RTL designer to understand design intent and clock structure, with CAD to understand and develop flow, and with Physical design team to close and sign-off timing. You ...
You will closely interact with RTL designer to understand design intent and clock structure, with CAD to understand and develop flow, and with Physical design team to close and sign-off timing. You ...
Orlando, FL · On-site
$127K - $155K/yr
In this role, you will be leading block and sub-system level pre-silicon RTL verification of ... Cross-functional (arch, u-arch, design, DV, SW) collaboration experience to converge on design/DV ...
Orlando, FL · On-site
$127K - $155K/yr
In this role, you will be leading block and sub-system level pre-silicon RTL verification of ... Cross-functional (arch, u-arch, design, DV, SW) collaboration experience to converge on design/DV ...
$127K - $155K/yr
In this role, you will be leading block and sub-system level pre-silicon RTL verification of ... Cross-functional (arch, u-arch, design, DV, SW) collaboration experience to converge on design/DV ...
$127K - $155K/yr
In this role, you will be leading block and sub-system level pre-silicon RTL verification of ... Cross-functional (arch, u-arch, design, DV, SW) collaboration experience to converge on design/DV ...
Miami, FL · On-site
$4.5K - $5.8K/wk
FPGA Engineers work closely with business leaders to design and deploy FPGA solutions that help ... Hardware Architecture, RTL Coding, Simulation, Systems Integration, Hardware Validation and Testing ...
Miami, FL · On-site
$4.5K - $5.8K/wk
FPGA Engineers work closely with business leaders to design and deploy FPGA solutions that help ... Hardware Architecture, RTL Coding, Simulation, Systems Integration, Hardware Validation and Testing ...
$60.2K - $67.1K
0% of jobs
$67.1K - $74K
0% of jobs
$74K - $80.9K
1% of jobs
$80.9K - $87.9K
0% of jobs
$87.9K - $94.8K
0% of jobs
$97.7K is the 25th percentile. Wages below this are outliers.
$94.8K - $101.7K
57% of jobs
$104.7K is the 75th percentile. Wages above this are outliers.
$101.7K - $108.7K
38% of jobs
$108.7K - $115.6K
0% of jobs
$115.6K - $122.5K
1% of jobs
$122.5K - $129.5K
1% of jobs
$129.5K - $136.4K
1% of jobs
$60.2K
$104.1K
$136.4K
An RTL (Register Transfer Level) Design job involves designing and implementing digital circuits using hardware description languages (HDLs) like Verilog or VHDL. RTL engineers translate high-level specifications into synthesizable logic, ensuring functionality, power efficiency, and performance. They collaborate with verification engineers to test and debug designs before fabrication. This role is crucial in developing ASICs, FPGAs, and other digital hardware components.
A typical day for an RTL Design engineer involves writing and optimizing RTL code, running simulations, debugging designs, and reviewing results from verification teams. Collaboration is key, as you will frequently interact with verification engineers, physical design teams, and architects to ensure the design meets both functional and performance requirements. You may also participate in design reviews, resolve issues found during testing, and work with project managers to meet deadlines. This cross-functional teamwork creates a dynamic environment where communication and problem-solving skills are highly valued, helping ensure the successful delivery of silicon products.
To thrive as an RTL Design engineer, you need a solid background in digital logic design, computer architecture, and proficiency in hardware description languages such as Verilog or VHDL, typically supported by a degree in electrical or computer engineering. Familiarity with EDA tools like Synopsys, Cadence, or Mentor Graphics, and experience with FPGA/ASIC flows, are highly valuable, as are relevant industry certifications. Strong problem-solving skills, attention to detail, and effective communication foster successful collaboration with verification and physical design teams. These skills are crucial for delivering robust, efficient hardware solutions in complex chip development projects.
The most popular types of Rtl Design jobs in Florida are:
For Rtl Design jobs in Florida, the most frequently searched job titles are:
The top searched job categories for Rtl Design jobs in Florida are:
$4.3K - $4.8K/wk
Other
Re-posted 2 days ago
At Citadel Securities, a leading global market maker, our team of FPGA Engineers work in small teams to create the next generation FPGA solutions to support ultra-low latency trading systems across the firm. FPGA Engineers work closely with business leaders to design and deploy FPGA solutions that help optimize trading system performance. As an intern, you’ll get to challenge the impossible in technology through an 11-week program that will allow you to collaborate and connect with senior team members. In addition, you’ll get the opportunity to network and socialize with peers throughout the internship. Your Objectives:
Your Skills & Talents:
Opportunities available in New York.
In accordance with applicable law, the base salary range for this role is $4,300 to $4,800 per week.
About Citadel SecuritiesCitadel Securities is the next-generation capital markets firm and a leading global market maker. We provide institutional and retail investors with the liquidity they need to trade a broad array of equity and fixed income products in any market condition. The brightest minds in finance, science and technology use powerful, advanced analytics to solve the market’s most critical challenges, turning big ideas into real-world outcomes.
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Finance and insurance
1,001 - 5,000 Employees
Miami, FL, US
2002
