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Remote Design Verification Engineer Jobs (NOW HIRING)

K2 Space

Principal ASIC Design Verification Engineer

OR · On-site +1

$190K - $285K/yr

The Role We are seeking a Principal ASIC Design Verification Engineer whose role will be to verify the functionality, performance, and robustness of our custom silicon designs. You will help define ...

IC Enable

RTL Design/AMS Verification Engineer

Richardson, TX · On-site +1

$122K - $149K/yr

We are seeking an experienced RTL Design / AMS Verification Engineer to support digital and mixed ... Remote Key Responsibilities * Develop, integrate, and verify Verilog RTL for digital and mixed ...

K2 Space

Senior ASIC Design Verification Engineer

OR · On-site +1

$170K - $250K/yr

The Role We are seeking a Senior ASIC Design Verification Engineer whose role will be to verify the functionality, performance, and robustness of our custom silicon designs. You will help define the ...

K2 Space

Principal ASIC Design Verification Engineer

$190K - $285K/yr

The Role We are seeking a Principal ASIC Design Verification Engineer whose role will be to verify the functionality, performance, and robustness of our custom silicon designs. You will help define ...

K2 Space

Senior ASIC Design Verification Engineer

$170K - $250K/yr

The Role We are seeking a Senior ASIC Design Verification Engineer whose role will be to verify the functionality, performance, and robustness of our custom silicon designs. You will help define the ...

Redolent, Inc.

US_West | Infrastructure Engineer_L3

$169K/yr

Marie.samayoa@capgemini.com SOC Design Verification Engineer Location: Redmond, WA Hybrid (Remote option allowed) Minimum Qualifications • Track record of 'first-pass success' in ASIC development ...

IC Enable

AMS Verification Engineer

Richardson, TX · On-site +1

$122K/yr

Richardson, TX (Hybrid Schedule, Remote considered based on experience and qualifications) What You ... Support design reviews, silicon readiness, bring-up planning, and product delivery What We're ...

Inherent Technologies

Design Verification

Chandler, AZ · Remote

$139K - $169K/yr

Experience with flow optimizations such as Grey/Black-boxing techniques Good at communicating requirements/issues with Implementation, PnR and Design teams. Working knowledge of Confluence ...

Nvidia

Senior ASIC Verification Engineer

OR · On-site +1

The complexity of the clocks and resets design has increased many folds. This requires ... Hands on experience in object-oriented programming * Prior design or verification experience at the ...

Nvidia

Senior ASIC Verification Engineer

OR · On-site +1

The complexity of the clocks and resets design has increased many folds. This requires ... verification process Hands on experience in object-oriented programming Prior design or ...

Apex Informatics

RTL Design and Verification

$139K - $169K/yr

Bachelor's degree in electrical engineering with 3+ experience or master's degree in electrical ... Micro-architecture definition of design features, test plan creation and functional verification.

Belcan

(Remote)Design Quality Engineer

$93K - $114K/yr

A remote Design Quality Engineer job is currently available at Belcan. This is a full-time, direct position. Great matching candidates, either local or remote, will need a Bachelor"s Degree in ...

Belcan

(Remote)Design Quality Engineer

$93K - $114K/yr

A remote Design Quality Engineer job is currently available at Belcan. This is a full-time, direct position. Great matching candidates, either local or remote, will need a Bachelor"s Degree in ...

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Remote Design Verification Engineer information

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$105.5K

$149.2K

$167K

How much do remote design verification engineer jobs pay per year?

As of Sep 8, 2026, the average yearly pay for remote design verification engineer in the United States is $149,150.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $166,000.00 per year, depending on experience, location, and employer.

What is a remote design verification engineer?

Remote Design Verification Engineers are professionals who work from a remote location to ensure that hardware designs, such as integrated circuits or systems on a chip (SoC), function correctly according to their specifications. They use simulation and verification tools to test digital designs, identify bugs, and work closely with design teams to resolve issues. Their responsibilities often include writing test benches, developing verification plans, and automating tests to improve efficiency. This role requires a strong background in hardware description languages like Verilog or VHDL, as well as experience with verification methodologies such as UVM or SystemVerilog.

What are the key skills and qualifications needed to thrive as a remote design verification engineer?

To thrive as a Remote Design Verification Engineer, you need a solid background in digital design, verification methodologies (such as UVM or SystemVerilog), and a relevant engineering degree. Proficiency in simulation tools (like VCS or ModelSim), scripting languages (Python or Perl), and version control systems is typically required. Exceptional problem-solving abilities, attention to detail, and strong communication skills are crucial for effective collaboration in a remote environment. These competencies ensure accurate verification, efficient workflow, and high-quality deliverables in complex hardware development projects.

What are some common challenges faced by remote design verification engineers, and how can they be addressed?

Remote Design Verification Engineers often encounter challenges related to communication and collaboration, especially when working with global teams across different time zones. Maintaining clear and frequent communication through project management tools and regular video meetings is essential. Additionally, ensuring access to secure and reliable simulation environments can be a hurdle, so familiarity with remote access protocols and cloud-based verification tools is beneficial. Proactively documenting verification processes and results also helps keep everyone aligned and facilitates smoother project progress.

What is the difference between Remote Design Verification Engineer vs Remote Test Engineer?

AspectRemote Design Verification EngineerRemote Test Engineer
CredentialsBachelor's in Electrical Engineering, Computer Engineering, or related field; knowledge of verification toolsBachelor's in Electrical Engineering, Computer Engineering, or related field; testing certifications beneficial
Work EnvironmentDesign labs, simulation environments, collaboration with design teamsTesting labs, field testing, collaboration with verification teams
Industry UsageSemiconductors, integrated circuits, hardware design companiesElectronics, hardware manufacturing, embedded systems companies

The Remote Design Verification Engineer focuses on verifying hardware designs through simulation and analysis before manufacturing, ensuring design correctness. In contrast, the Remote Test Engineer primarily tests finished products or prototypes to validate functionality and performance. Both roles require technical expertise and collaboration but differ in their project stages and focus areas.

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Remote Design Verification Engineer jobs near you
Infographic showing various Remote Design Verification Engineer job openings in the United States as of September 2026, with employment types broken down into 1% Internship, 89% Full Time, 7% Part Time, and 3% Contract. Highlights an 81% Physical, 4% Hybrid, and 15% Remote job distribution, with an average salary of $149,150 per year, or $71.7 per hour.

Principal ASIC Design Verification Engineer

K2 Space

OR • On-site, Remote

$190K - $285K/yr

Full-time

Medical, Dental, Vision, Life, PTO

Re-posted 13 days ago

Job description

The Role 

We are seeking a Principal ASIC Design Verification Engineer whose role will be to verify the functionality, performance, and robustness of our custom silicon designs. You will help define the verification approach, contribute to methodology, and work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a hands-on role with high ownership, deep technical engagement, and the opportunity to shape first-generation silicon. 

Responsibilities 

  • Develop and execute verification plans for block-level, subsystem-level, and full-chip environments.
  • Build SystemVerilog/UVM test benches, including agents, monitors, scoreboards, checkers, and coverage models.
  • Write SystemVerilog Assertions (SVA) and integrate formal verification where appropriate.
  • Drive constrained-random and directed testing strategies to validate functionality, corner cases, and stress scenarios.
  • Run simulations, triage failures, drive root-cause analysis, and collaborate with RTL designers to resolve issues.
  • Implement and maintain functional coverage, code coverage, assertion coverage, and ensure coverage closure for sign-off.
  • Manage regression testing, simulation farms, and CI pipelines to ensure high test throughput and fast debug iterations.
  • Participate in design reviews, microarchitecture discussions, and influence design-for-verification (DFV) best practices.
  • Work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers to ensure end-to-end coverage and test.
  • Support silicon bring-up and post-silicon validation through test reuse, diagnostics, and debug analysis.
  • Participate in ASIC team interviews.
  • Drive advancement of DV methodologies and improvements.
  • Manage external IP providers and verification partners when needed.
  • Take lead on large and/or complex systems. 

Qualifications 

  • B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field.
  • 10+ years of experience in ASIC/SoC verification.
  • Solid understanding of SystemVerilog, digital logic, RTL design, DFT, and hardware design and verification flows.
  • Proficiency with several simulation (VCS, Xcelium, Questa), waveform debug (Verdi, SimVision), coverage tools, and scripting languages (ex: Python, Perl, TCL).
  • Experience with test planning, UVM-based testbench development, constrained-random testing, functional coverage, and SystemVerilog assertions.
  • Experience with regression management, coverage analysis, revision control (ex: Git), CI/CD automation, and gate-level simulation.
  • Experience with developing and integrating reference models.
  • Experience with embedded processor-based designs and firmware/bare metal coding (ex: C, C++).
  • Understanding of many industry-standard interfaces (ex: APB/AHB/AXI).
  • Involvement in post-silicon validation planning and execution. 

Nice to Have

  • Experience with low power verification.
  • Experience with analog behavioral models.
  • Familiarity with physical design flows.
  • Experience working in cross-functional, geographically distributed teams.
  • Experience in space, telecom, or RF/digital mixed systems is a plus. 

Compensation and Benefits:

  • Base salary range for this role is $190,000 - $285,000 + equity in the company
  • Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
  • Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks
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About K2 Space

Sourced by ZipRecruiter

Industry

Guided missile and space vehicle manufacturing

Company size

11 - 50 Employees

Headquarters location

Los Angeles, CA, US

Year founded

2022

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