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Manager Digital Verification Engineer Jobs (NOW HIRING)

Teradyne

Digital Verification Engineer Lead

Tualatin, OR · On-site

$155 - $248/hr

Opportunity Overview Act as a digital functional verification technical lead responsible for the ... Master's Degree or equivalent in Electrical Engineering/Computer Engineering/Computer Science or ...

Apple

Wireless Radio Verification Engineer

San Diego, CA · On-site

$144K/yr

As a Wireless Radio Verification Engineer, you'll ensure first-time-right silicon success through ... data paths, power management, and co-existence mechanisms. This role emphasizes digital ...

Draper

Senior UVM Digital Verification Engineer

Cambridge, MA · On-site

$113K - $153K/yr

... Digital Verification Engineer to tackle novel verification challenges in FPGAs and ASICs. In this ... time management skills with the proven ability to meet deadlines. • Demonstrated knowledge of ...

Draper

Senior UVM Digital Verification Engineer

Cambridge, MA · On-site

$114K - $156K/yr

... Digital Verification Engineer to tackle novel verification challenges in FPGAs and ASICs. In this ... Excellent time management skills with the proven ability to meet deadlines. Demonstrated knowledge ...

Optimalsemi

Design Verification Engineer

Dallas, TX · On-site

$120 - $150/hr

Fiori Technology Solutions is currently hiring for a Design Verification Engineer. This is fulltime ... ADCs/DACs, OSCs, clock trees, power management circuits together with digital Ips * Basic ...

NXP Semiconductors

Digital Verification

Austin, TX · On-site

$121K/yr

Performs semiconductor design engineering duties including design, development, and testing for ... Verification Methodology); 4. Computer Architecture; 5. Digital Design with FGPA; 6. VLSI System ...

NXP Semiconductors

Digital Verification

Austin, TX · On-site

$165K/yr

Perform professional verification engineering duties in furtherance of architecture and RTL design. Responsible for development of models or verification environment required specifically for Digital ...

NXP Semiconductors N.V.

Digital Verification

Austin, TX · On-site

$165K/yr

Perform professional verification engineering duties in furtherance of architecture and RTL design. Responsible for development of models or verification environment required specifically for Digital ...

NXP Semiconductors N.V.

Digital Verification

Austin, TX · On-site

$121K/yr

Performs semiconductor design engineering duties including design, development, and testing for ... Verification Methodology); 4. Computer Architecture; 5. Digital Design with FGPA; 6. VLSI System ...

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Manager Digital Verification Engineer information

See salary details

$105.5K

$149.2K

$167K

How much do manager digital verification engineer jobs pay per year?

As of Aug 30, 2026, the average yearly pay for manager digital verification engineer in the United States is $149,150.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $166,000.00 per year, depending on experience, location, and employer.

What does a manager digital verification engineer do?

A Manager Digital Verification Engineer leads a team responsible for verifying the functionality and performance of digital hardware designs, ensuring they meet specifications before production. This role involves overseeing the development and execution of verification plans using simulation, emulation, and formal verification tools. The manager coordinates with design, validation, and project management teams to deliver high-quality, bug-free silicon products on schedule. They also mentor engineers, optimize verification methodologies, and maintain project documentation.

How does a manager digital verification engineer typically balance hands-on technical verification work with team leadership responsibilities?

A Manager Digital Verification Engineer often splits their time between overseeing the technical direction of verification projects and managing a team of engineers. While they remain involved in high-level planning, reviewing verification strategies, and resolving complex technical issues, they also focus on mentoring team members, conducting performance reviews, and aligning resources to project timelines. The role requires strong organizational skills to ensure project milestones are met without sacrificing team development or quality. Regular collaboration with design, validation, and project management teams is essential to ensure seamless integration and product delivery.

What are the key skills and qualifications needed to thrive as a manager digital verification engineer, and why are they important?

To thrive as a Manager Digital Verification Engineer, you need a deep understanding of digital design verification, expertise in SystemVerilog or UVM methodologies, and a relevant engineering degree. Familiarity with industry-standard EDA tools like Synopsys VCS, Cadence Xcelium, and scripting languages such as Python or Perl is critical, along with experience in project management. Strong leadership, communication, and problem-solving abilities help you effectively guide teams and collaborate across departments. These skills ensure efficient, high-quality verification processes, timely project delivery, and successful team performance in complex semiconductor development environments.

What is the difference between Manager Digital Verification Engineer vs Digital Verification Engineer?

AspectManager Digital Verification EngineerDigital Verification Engineer
CredentialsBachelor's/Master's in Electrical Engineering, VLSI, or related; often with leadership experienceBachelor's/Master's in Electrical Engineering, VLSI, or related; no managerial experience required
Work EnvironmentLeads verification teams, manages projects, coordinates with design teamsPerforms verification tasks, runs simulations, develops testbenches
Industry UsageCommon in semiconductor, electronics, and chip design companiesWidely used in similar industries for verification roles

The main difference is that a Manager Digital Verification Engineer oversees verification teams and projects, focusing on leadership and coordination, while a Digital Verification Engineer primarily executes verification tasks and develops test environments. The managerial role involves more strategic planning, resource management, and team leadership, whereas the verification engineer role is more technical and hands-on.

What cities are hiring for Manager Digital Verification Engineer jobs?

Cities with the most Manager Digital Verification Engineer job openings:

What are the most commonly searched types of Digital Verification Engineer jobs?

The most popular types of Digital Verification Engineer jobs are:

What states have the most Manager Digital Verification Engineer jobs?

States with the most job openings for Manager Digital Verification Engineer jobs include:

Manager Digital Verification Engineer jobs near you
Infographic showing various Manager Digital Verification Engineer job openings in the United States as of August 2026, with employment types broken down into 88% Full Time, 11% Part Time, and 1% Contract. Highlights an 80% Physical, 2% Hybrid, and 18% Remote job distribution, with an average salary of $149,150 per year, or $71.7 per hour.

Lead Digital Verification Engineer

Efficient Computer

San Jose, CA • On-site

$159K - $194K/yr

Full-time

Retirement

Re-posted 10 days ago

Job description

Efficient is developing the world's most energy-efficient general-purpose computer processor. Efficient's patented technology uses 100x less energy than state of the art commercially available ultra-low-power processors and is programmable using standard high-level programming languages and AI/ML frameworks. This level of efficiency makes perpetual, pervasive intelligence possible: run AI/ML continuously on a AA battery for 5-10 years. Our platform's unprecedented level of efficiency enables IoT devices to intelligently capture and curate first-party data to drive the next major computing revolution
We are looking for an experienced Design Verification Lead to drive the functional verification of complex SoC/IP designs from specification through tapeout in a newly formed hardware engineering organization. You will own the verification strategy, define methodology standards, build and guide a team of verification engineers, and serve as the final authority on verification quality and sign-off readiness. This role demands a strong blend of technical depth in modern verification methodologies (UVM, embedded C and compiler generated trace driven testing) and the leadership ability to execute across a multi-block chip program on schedul.e The DV Lead will help shape our internal processes for building robust and verified designs, including the company's second product line, which will scale computing performance and capability, while improving energy efficiency.
This is a unique opportunity to have an influence on our products and processes as we move from the initial stages of product development to market release and scaled volume production. Join our team and help us shape the future of computing at the edge and beyond!
Key Responsibilities
  • Define the end-to-end verification strategy across block, subsystem, and full-chip levels aligned with tapeout milestones
  • Author and review verification plans mapping specifications to features, stimulus strategies(traditional stimulus generation, compiler driven), coverage goals, and sign-off criteria
  • Architect scalable UVM-based testbench environments including agents, scoreboards, reference models, and coverage monitors
  • Drive constrained-random stimulus development targeting protocol interactions, concurrency, error injection, and corner cases
  • Define and close functional coverage models through systematic hole analysis, targeted tests, seed optimization, and regression tuning
  • Deploy SystemVerilog Assertions for protocol compliance, interface checks, and design invariants across all simulation runs
  • Lead full-chip verification including boot sequences, interrupt handling, DMA flows, power-on reset, and multi-block interactions
  • Ensure CDC, RDC, and multi-power-domain verification in coordination with specialist tools and teams
  • Debug complex simulation failures spanning multi-block interactions, protocol violations, race conditions, and timing-dependent corner cases
  • Own the bug lifecycle - triage, prioritization, tracking, fix verification, and cross-functional resolution with RTL designers and architects
  • Manage the regression framework - defining suites, maintaining stability, optimizing throughput, and integrating with CI/CD pipelines
  • Coordinate simulation-to-emulation handoff ensuring verification collateral transitions effectively to emulation environments
  • Collaborate cross-functionally with Compiler Team, RTL design, DFT, physical design, and post-silicon validation teams
  • Lead, mentor, and grow the verification engineering team while maintaining a high quality bar through rigorous reviews
  • Represent verification readiness in tapeout sign-off reviews and program-level decisions
  • Support running gate-level simulations as part of design signoff.
  • Assist in building a verification dashboard to quickly understand where a design is in the verification process and to identify regressions.

Required Qualifications & Experience
  • Education: Bachelor's or Master's/PhD degree in Electrical Engineering, Computer Engineering, or a related field.
  • Experience: 10+ years of progressive experience in ASIC/SoC design verification, with at least 3 years in a lead role owning verification strategy, sign-off, and team execution.
  • UVM Mastery: Deep expertise in UVM-based testbench architecture and constrained-random verification methodology - not just usage, but architectural decision-making and optimization.
  • SystemVerilog: Advanced proficiency in SystemVerilog for verification including classes, constraints, functional coverage, assertions (SVA), interfaces, and packages.
  • Coverage Closure: Demonstrated track record of driving functional and code coverage to tapeout sign-off on complex, multi-million-gate SoC/ASIC designs.
  • Debug Skills: Proven ability to debug deeply complex simulation failures spanning multiple design blocks, protocols, and abstraction levels.
  • SoC Architecture: Strong understanding of modern SoC building blocks - processors (ARM, RISC-V), interconnects (AMBA AXI/ACE/CHI), memory controllers, DMA engines, interrupt controllers, and standard peripherals.
  • Scripting & Automation: Proficiency in Python, Perl, or Tcl for test automation, log analysis, coverage post-processing, and regression flow development.
  • Communication: Clear and effective communication of verification status, risk, and trade-offs to technical peers and program leadership.

We offer a competitive salary for this role, generally ranging from $200,000 to $230,000, along with meaningful equity and comprehensive benefits. The final compensation package will be based on your experience and location, with some flexibility to ensure we align with the right candidate.
Why Join Efficient?
Efficient offers a competitive compensation and benefits package, including 401K match, company-paid benefits, equity program, paid parental leave, and flexibility. We are committed to personal and professional development and strive to grow together as people and as a company.

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