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Locum Asic Rtl Design Engineer Jobs in Seattle, WA

You will work closely with architecture, RTL design, DFT, DV, firmware, physical design, and ... the ASIC organization. * Work with RTL engineers to compile, map, and optimize designs for ...

The Role We are seeking a Senior ASIC Physical Design Engineer to help implement advanced SoCs that ... RTL, verification, and packaging teams. You'll be a key contributor in achieving timing closure ...

FPGA Engineer, Amazon LEO OISL

Redmond, WA · On-site

$145K - $187K/yr

... RTL Design-Physical Implementation-Timing Closure-Simulation Validation- Lab Based Silicon ... with ASIC/FPGA design and verification tools - 3+ years of experience in ASIC/FPGA design ...

Craft micro-architecture specification, implement in high-quality RTL, and deliver a fully verified ... Deep understanding of ASIC design flows and methodology * Strong analytical and interpersonal ...

FPGA Engineer, Amazon LEO OISL

Redmond, WA · On-site

$145K - $187K/yr

... design engineer will work with systems teams to define/develop/implement/test/release FPGA based ... RTL Design-Physical Implementation-Timing Closure-Simulation Validation- Lab Based Silicon ...

Showing results 21-40

Locum Asic Rtl Design Engineer information

See Seattle, WA salary details

$107K

$170.9K

$229.9K

How much do locum asic rtl design engineer jobs pay per year?

As of Aug 11, 2026, the average yearly pay for locum asic rtl design engineer in Seattle, WA is $170,926.00, according to ZipRecruiter salary data. Most workers in this role earn between $149,600.00 and $204,800.00 per year, depending on experience, location, and employer.

What is the difference between Locum Asic Rtl Design Engineer vs Contract Asic Rtl Design Engineer?

AspectLocum Asic Rtl Design EngineerContract Asic Rtl Design Engineer
CredentialsTypically requires relevant engineering degrees and RTL design experienceSimilar credentials, often with specific RTL design certifications
Work EnvironmentTemporary, short-term assignments often in multiple locationsProject-based roles, usually in a fixed location or remote
Employer UsageUsed by agencies or companies needing immediate, short-term expertiseEngaged by companies or staffing agencies for project-specific work

Both roles involve RTL design skills for ASIC development, but a Locum Asic Rtl Design Engineer typically fills short-term, temporary positions, often through staffing agencies, while a Contract Asic Rtl Design Engineer is engaged for specific projects with defined durations. The main difference lies in the nature and duration of employment, but both require similar technical credentials and work environments.

What are the most commonly searched types of Asic Rtl Design Engineer jobs in Seattle, WA? The most popular types of Asic Rtl Design Engineer jobs in Seattle, WA are:
What are popular job titles related to Locum Asic Rtl Design Engineer jobs in Seattle, WA? For Locum Asic Rtl Design Engineer jobs in Seattle, WA, the most frequently searched job titles are:
What job categories do people searching Locum Asic Rtl Design Engineer jobs in Seattle, WA look for? The top searched job categories for Locum Asic Rtl Design Engineer jobs in Seattle, WA are:
Infographic showing various Locum Asic Rtl Design Engineer job openings in Seattle, WA as of August 2026, with employment types broken down into 1% Internship, 86% Full Time, 8% Part Time, and 5% Contract. Highlights an 86% Physical, 4% Hybrid, and 10% Remote job distribution, with an average salary of $170,926 per year, or $82.2 per hour.

Senior ASIC Physical Design Engineer

K2 Space

Seattle, WA

$170K - $250K/yr

Full-time

Medical, Dental, Vision, Life, PTO

Re-posted 10 days ago


Job description

The Role 

We are seeking a Senior ASIC Physical Design Engineer to help implement advanced SoCs that power next-generation satellite and space systems. In this role, you will contribute to the full physical design flow-from synthesis to GDSII-working closely with architecture, RTL, verification, and packaging teams. You'll be a key contributor in achieving timing closure, optimizing PPA, and supporting design integration with external partners. You will be part of a collaborative design team developing state-of-the-art mixed-signal SoCs to be hosted on some of the largest, most powerful, rapidly designed and rapidly manufactured satellites ever deployed in space. In your first 6 months, you will develop and implement new SoC sub-systems for satellite communications and beyond. In your first two years, you will have contributed to developing cutting-edge SoCs that will fly in space. 

Responsibilities 

  • Execute the complete physical design flow for complex SoC blocks and top-level integration, including synthesis, floorplanning, place & route, CTS, STA, and physical verification. 
  • Perform timing closure and optimization across multiple corners and modes using industry-standard tools. 
  • Collaborate with front-end, verification, and DFT teams to ensure clean handoff and predictable convergence. 
  • Work with external physical design service providers and internal leads to review deliverables, resolve issues, and ensure schedule alignment. 
  • Develop and maintain scripts and automation to improve flow efficiency and consistency. 
  • Support physical sign-off activities including DRC/LVS, IR drop, EM, and power analysis. 
  • Assist in chip-level integration, ECOs, and tapeout preparation. 
  • Contribute to methodology development, tool evaluation, and flow documentation. 
  • Support your product through production and spaceflight.  

Required Qualifications 

  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field. 
  • 5-10 years of experience in ASIC physical design for complex SoCs. 
  • Hands-on experience with industry-standard tools (Synopsys ICC2/Fusion Compiler, Cadence Innovus, or equivalent). 
  • Strong understanding of timing analysis, power optimization, and physical verification flows. 
  • Experience with hierarchical or flat SoC design methodologies. 
  • Familiarity with FinFET technologies. 
  • Working knowledge of DFT, UPF/CPF power intent, and ECO implementation. 
  • Strong problem-solving skills and ability to work cross-functionally in fast-paced environments. 

Preferred Qualifications 

  • Exposure to radiation-hardened or space-qualified ASICs. 
  • Experience with chip-package co-design or advanced packaging (2.5D/3D). 
  • Familiarity with physical design service vendor management or offshore collaboration. 
  • Experience with sign-off through TSMC. 
  • Experience with Gate-All-Around technologies.  
  • Experience working in cross-functional, geographically distributed teams. 

Compensation and Benefits:

  • Base salary range for this role is $170,000 - $250,000 + equity in the company
  • Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
  • Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks

K2 Space logo

About K2 Space

Sourced by ZipRecruiter

Industry

Guided missile and space vehicle manufacturing

Company size

11 - 50 Employees

Headquarters location

Los Angeles, CA, US

Year founded

2022