Job Title: "Senior Layout Design Engineer" Location: San Jose, CA (Onsite, 5 days a week) Duration: Long Term Description Client is looking for a talent that has strong background and hands-on ...
Job Title: "Senior Layout Design Engineer" Location: San Jose, CA (Onsite, 5 days a week) Duration: Long Term Description Client is looking for a talent that has strong background and hands-on ...
The Senior GT Design Engineer will be responsible for the development of the overall gas turbine layout design and component integration Responsibilities - Perform the overall GT layout design with ...
The Senior GT Design Engineer will be responsible for the development of the overall gas turbine layout design and component integration Responsibilities - Perform the overall GT layout design with ...
Layout Design Engineer
Austin, TX · On-site
The Role In this role, you will work closely with design engineering to complete the layout and verification of high-performance mixed-signal CMOS Integrated Circuits using Cadence Virtuoso XL and ...
Layout Design Engineer
Austin, TX · On-site
The Role In this role, you will work closely with design engineering to complete the layout and verification of high-performance mixed-signal CMOS Integrated Circuits using Cadence Virtuoso XL and ...
Analog Layout Design Engineer
Santa Clara, CA · On-site
$237K/yr
Analog Layout Design Engineer Job Location: Santa Clara, CA (Onsite for 5 days a week) Job Type: Long-term contract Duration: 12 months Minimum Qualifications * The ideal candidate should have a ...
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Analog Layout Design Engineer
Santa Clara, CA · On-site
$237K/yr
Analog Layout Design Engineer Job Location: Santa Clara, CA (Onsite for 5 days a week) Job Type: Long-term contract Duration: 12 months Minimum Qualifications * The ideal candidate should have a ...
The team has an exciting opportunity for a IC Layout Design Engineer V to join our diverse team executing full-custom integrated circuit development with specific responsibility for driving the ...
The team has an exciting opportunity for a IC Layout Design Engineer V to join our diverse team executing full-custom integrated circuit development with specific responsibility for driving the ...
Digital Layout Design Engineer
Austin, TX · On-site
... engineering specifications and expectations. -Use advanced CAD tools, mask design knowledge to layout corrections and robust physical design representation of circuits. Minimum Qualifications ...
Digital Layout Design Engineer
Austin, TX · On-site
... engineering specifications and expectations. -Use advanced CAD tools, mask design knowledge to layout corrections and robust physical design representation of circuits. Minimum Qualifications ...
Analog Layout Design Engineer Job location: Santa Clara, CA, 95054 Job Duration: 3 Months, Contract to Hire * Experience with layout of cutting-edge high-performance, high-speed CMOS integrated ...
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Analog Layout Design Engineer Job location: Santa Clara, CA, 95054 Job Duration: 3 Months, Contract to Hire * Experience with layout of cutting-edge high-performance, high-speed CMOS integrated ...
Digital Layout Design Engineer
Austin, TX · On-site
... engineering specifications and expectations. -Use advanced CAD tools, mask design knowledge to layout corrections and robust physical design representation of circuits. Minimum Qualifications ...
Digital Layout Design Engineer
Austin, TX · On-site
... engineering specifications and expectations. -Use advanced CAD tools, mask design knowledge to layout corrections and robust physical design representation of circuits. Minimum Qualifications ...
Digital Layout Design Engineer
Austin, TX · On-site
$140 - $200/hr
Exceed engineering specifications and expectations. * Use advanced CAD tools, mask design knowledge to layout corrections and robust physical design representation of circuits. MINIMUM QUALIFICATIONS ...
Digital Layout Design Engineer
Austin, TX · On-site
$140 - $200/hr
Exceed engineering specifications and expectations. * Use advanced CAD tools, mask design knowledge to layout corrections and robust physical design representation of circuits. MINIMUM QUALIFICATIONS ...
Digital Layout Design Engineer
$166K - $296K/yr
... design team to plan, schedule work and negotiate layout tradeoffs as needed. - Interpretation of LVS, DRC and ERC report to find the fastest way to complete layouts. - Exceed engineering ...
Digital Layout Design Engineer
$166K - $296K/yr
... design team to plan, schedule work and negotiate layout tradeoffs as needed. - Interpretation of LVS, DRC and ERC report to find the fastest way to complete layouts. - Exceed engineering ...
Digital Layout Design Engineer
$137K - $250K/yr
... design team to plan, schedule work and negotiate layout tradeoffs as needed. - Interpretation of LVS, DRC and ERC report to find the fastest way to complete layouts. - Exceed engineering ...
Digital Layout Design Engineer
$137K - $250K/yr
... design team to plan, schedule work and negotiate layout tradeoffs as needed. - Interpretation of LVS, DRC and ERC report to find the fastest way to complete layouts. - Exceed engineering ...
Digital Layout Design Engineer
$166K - $296K/yr
... design team to plan, schedule work and negotiate layout tradeoffs as needed. - Interpretation of LVS, DRC and ERC report to find the fastest way to complete layouts. - Exceed engineering ...
Digital Layout Design Engineer
$166K - $296K/yr
... design team to plan, schedule work and negotiate layout tradeoffs as needed. - Interpretation of LVS, DRC and ERC report to find the fastest way to complete layouts. - Exceed engineering ...
Digital Layout Design Engineer
$166K - $296K/yr
... design team to plan, schedule work and negotiate layout tradeoffs as needed. - Interpretation of LVS, DRC and ERC report to find the fastest way to complete layouts. - Exceed engineering ...
Digital Layout Design Engineer
$166K - $296K/yr
... design team to plan, schedule work and negotiate layout tradeoffs as needed. - Interpretation of LVS, DRC and ERC report to find the fastest way to complete layouts. - Exceed engineering ...
Digital Layout Design Engineer
$137K - $250K/yr
... design team to plan, schedule work and negotiate layout tradeoffs as needed. - Interpretation of LVS, DRC and ERC report to find the fastest way to complete layouts. - Exceed engineering ...
Digital Layout Design Engineer
$137K - $250K/yr
... design team to plan, schedule work and negotiate layout tradeoffs as needed. - Interpretation of LVS, DRC and ERC report to find the fastest way to complete layouts. - Exceed engineering ...
Digital Layout Design Engineer
$137K - $250K/yr
... design team to plan, schedule work and negotiate layout tradeoffs as needed. - Interpretation of LVS, DRC and ERC report to find the fastest way to complete layouts. - Exceed engineering ...
Digital Layout Design Engineer
$137K - $250K/yr
... design team to plan, schedule work and negotiate layout tradeoffs as needed. - Interpretation of LVS, DRC and ERC report to find the fastest way to complete layouts. - Exceed engineering ...
Digital Layout Design Engineer
$137K - $250K/yr
... design team to plan, schedule work and negotiate layout tradeoffs as needed. - Interpretation of LVS, DRC and ERC report to find the fastest way to complete layouts. - Exceed engineering ...
Digital Layout Design Engineer
$137K - $250K/yr
... design team to plan, schedule work and negotiate layout tradeoffs as needed. - Interpretation of LVS, DRC and ERC report to find the fastest way to complete layouts. - Exceed engineering ...
AMR Layout Design Engineer
Troy, MI · On-site
As an AMR Layout Design Engineer will be responsible for the engineering design and deployment of AMR systems at customer facilities, validating and ensuring the systems as installed are safe and in ...
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AMR Layout Design Engineer
Troy, MI · On-site
As an AMR Layout Design Engineer will be responsible for the engineering design and deployment of AMR systems at customer facilities, validating and ensuring the systems as installed are safe and in ...
Hardware Design Engineer - PCB layout
Warren, MI · On-site
$98.30 - $177.80/hr
Hardware Design Engineer - PCB layoutSkip to main content#Hardware Design Engineer - PCB layout page is loaded## Hardware Design Engineer - PCB layoutApplyremote type: Hybridlocations: Warren ...
Hardware Design Engineer - PCB layout
Warren, MI · On-site
$98.30 - $177.80/hr
Hardware Design Engineer - PCB layoutSkip to main content#Hardware Design Engineer - PCB layout page is loaded## Hardware Design Engineer - PCB layoutApplyremote type: Hybridlocations: Warren ...
AMR Layout Design Engineer
Troy, MI · On-site
As an AMR Layout Design Engineer will be responsible for the engineering design and deployment of AMR systems at customer facilities, validating and ensuring the systems as installed are safe and in ...
AMR Layout Design Engineer
Troy, MI · On-site
As an AMR Layout Design Engineer will be responsible for the engineering design and deployment of AMR systems at customer facilities, validating and ensuring the systems as installed are safe and in ...
Digital Layout Design Engineer
$166K - $296K/yr
... design team to plan, schedule work and negotiate layout tradeoffs as needed. - Interpretation of LVS, DRC and ERC report to find the fastest way to complete layouts. - Exceed engineering ...
Digital Layout Design Engineer
$166K - $296K/yr
... design team to plan, schedule work and negotiate layout tradeoffs as needed. - Interpretation of LVS, DRC and ERC report to find the fastest way to complete layouts. - Exceed engineering ...
Layout Design Engineer information
See salary details
$45K - $57.8K
4% of jobs
$57.8K - $70.5K
2% of jobs
$70.5K - $83.3K
12% of jobs
$93.7K is the 25th percentile. Wages below this are outliers.
$83.3K - $96.1K
9% of jobs
$96.1K - $108.9K
11% of jobs
The median wage is $120.7K / yr.
$108.9K - $121.6K
14% of jobs
$121.6K - $134.4K
22% of jobs
$136.8K is the 75th percentile. Wages above this are outliers.
$134.4K - $147.2K
9% of jobs
$147.2K - $160K
9% of jobs
$160K - $172.7K
3% of jobs
$172.7K - $185.5K
6% of jobs
$45K
$120.8K
$185.5K
How much do layout design engineer jobs pay per year?
What is a layout design engineer?
A Layout Design Engineer is responsible for designing and optimizing the physical layout of integrated circuits (ICs) in semiconductor chips. They work closely with circuit designers to ensure that the layout meets performance, power, and area constraints while adhering to manufacturing and design rules. Their role involves using EDA tools for placement, routing, and verification of chip layouts. They also conduct design rule checks (DRC) and layout versus schematic (LVS) verification to ensure design accuracy.
What are the key skills and qualifications needed to thrive as a layout design engineer?
To thrive as a Layout Design Engineer, you need strong skills in electronic circuit design, physical layout principles, and a background in electrical or electronics engineering, typically supported by a relevant bachelor's degree. Proficiency with EDA tools such as Cadence, Mentor Graphics, or Synopsys, and knowledge of industry standards (e.g., IPC) are essential. Exceptional attention to detail, problem-solving, and effective teamwork and communication skills help set candidates apart. These capabilities ensure precise, manufacturable layouts and smooth collaboration with multidisciplinary teams to meet project goals and deadlines.
What does a layout design engineer do?
A typical day for a Layout Design Engineer involves translating schematic designs into detailed physical layouts using specialized CAD tools, collaborating closely with circuit designers to optimize for performance and manufacturability. You may spend time reviewing design rule checks (DRC), participating in team meetings to discuss project progress or resolve technical challenges, and coordinating with fabrication or test engineers to ensure successful implementation. The role requires both independent focus and frequent teamwork, offering a dynamic mix of technical and collaborative tasks. Depending on the company, you might also be involved in process improvement initiatives or mentoring junior engineers as you gain experience.

Job description
Job Description:
Job Title: "Senior Layout Design Engineer"
Location: San Jose, CA (Onsite, 5 days a week)
Duration: Long Term
Description
Client is looking for a talent that has strong background and hands-on experience on RF/Analog circuit layout design. The candidate will be developing next-generation RF transceivers and mixed-signal circuits for wireless communication systems along with circuit designers.
Requirements
- Associate and Bachelor's Degree with 10+ years of relevant industry experience in Electrical Engineering, Technical, or related field preferred.
- Extensive experience in analog/mixed-signal layout design of deep submicron CMOS circuits and recent experience on advance nodes including FinFET technologies.
- High level of proficiency in interpretation of CALIBRE DRC, ERC, LVS, reports.
- Extensive experience in analog/RF related circuit layout, including LNA/PA/PLLs and etc.
- High level of proficiency in CADENCE or MENTOR GRAPHICS layout tools.
- Good communication skills with design leads as well as engineers for schedule planning.
- Being able to lead a small group of layout engineers to deliver a successful tapeout.
- Programming knowledge in SKILL, Perl, and/or Python is a bonus.
- You re inclusive, adapting your style to the situation and diverse global norms of our people.
- An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
- You re collaborative, building relationships, humbly offering support and openly welcoming approaches.
- Innovative and creative, you proactively explore new ideas and adapt quickly to change.
About Xoriant
Sourced by ZipRecruiter
Industry
It services
Company size
1,001 - 5,000 Employees
Headquarters location
Sunnyvale, CA, US
Year founded
1990