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Internship Asic Rtl Design Engineer Jobs in Seattle, WA

K2 Space

Senior ASIC Emulation Engineer

Seattle, WA

$170K - $250K/yr

You will work closely with architecture, RTL design, DFT, DV, firmware, physical design, and ... the ASIC organization. * Work with RTL engineers to compile, map, and optimize designs for ...

K2 Space

Senior ASIC Physical Design Engineer

Seattle, WA · On-site

$170K - $250K/yr

The Role We are seeking a Senior ASIC Physical Design Engineer to help implement advanced SoCs that ... RTL, verification, and packaging teams. You'll be a key contributor in achieving timing closure ...

Amazon

FPGA Engineer, Amazon LEO OISL

Redmond, WA · On-site

$145K - $187K/yr

... RTL Design-Physical Implementation-Timing Closure-Simulation Validation- Lab Based Silicon ... with ASIC/FPGA design and verification tools - 3+ years of experience in ASIC/FPGA design ...

Microsoft

Senior Silicon Design Engineer

Redmond, WA · On-site

$119K - $234K/yr

... Level (RTL) design, synthesis/Lint/CDC/FEV and System on Chip (SOC) integration on different ... Integrated Circuits (ASIC)/SOC designs. * 4+ years expertise in Digital Design including ...

Nvidia

Senior Digital Design Engineer

Redmond, WA · On-site

Craft micro-architecture specification, implement in high-quality RTL, and deliver a fully verified ... Deep understanding of ASIC design flows and methodology * Strong analytical and interpersonal ...

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All JobsAsic Rtl Design Engineer JobsInternship Asic Rtl Design Engineer JobsInternship Asic Rtl Design Engineer Jobs in Seattle, WA

Internship Asic Rtl Design Engineer information

See Seattle, WA salary details

$107K

$170.9K

$229.9K

How much do internship asic rtl design engineer jobs pay per year?

As of Aug 9, 2026, the average yearly pay for internship asic rtl design engineer in Seattle, WA is $170,926.00, according to ZipRecruiter salary data. Most workers in this role earn between $149,600.00 and $204,800.00 per year, depending on experience, location, and employer.

What does an internship ASIC RTL design engineer do?

As an ASIC RTL Design Engineering intern, you'll typically work on tasks such as writing and verifying RTL code using languages like Verilog or VHDL, assisting with simulation and debugging, and collaborating closely with senior engineers on real design blocks. Interns often participate in design reviews, update documentation, and may get hands-on experience with synthesis and timing analysis tools. This role is highly collaborative and provides exposure to the complete ASIC development cycle, making it an excellent opportunity to build foundational skills and gain insight into industry-standard methodologies.

What are the key skills and qualifications needed to thrive as an internship ASIC RTL design engineer?

To thrive as an Internship ASIC RTL Design Engineer, you need a solid understanding of digital logic design, computer architecture, and proficiency in HDL languages like Verilog or VHDL, typically supported by coursework in electrical or computer engineering. Familiarity with industry-standard EDA tools such as Synopsys, Cadence, or Mentor Graphics, and simulation environments is highly valuable. Strong analytical thinking, attention to detail, and effective communication skills help interns collaborate with teams and learn quickly in a fast-paced environment. These skills and qualities are essential for contributing to complex chip design projects and ensuring accuracy and efficiency in RTL development.

What is an internship ASIC RTL design engineer?

An Internship ASIC RTL (Register Transfer Level) Design Engineer is a student or recent graduate who assists in designing and developing digital integrated circuits (ICs) using hardware description languages like Verilog or VHDL. They work under the guidance of senior engineers to create, simulate, and verify RTL code for ASIC (Application Specific Integrated Circuit) projects. The role provides hands-on experience with the chip design process, including synthesis, timing analysis, and verification. Interns gain valuable exposure to industry-standard tools and methodologies, helping them prepare for a full-time engineering career.

What is the difference between Internship Asic Rtl Design Engineer vs Asic Verification Engineer?

AspectInternship Asic Rtl Design EngineerAsic Verification Engineer
CredentialsTypically pursuing or recently completed a degree in Electrical Engineering or Computer EngineeringSimilar educational background, often with additional coursework in verification methodologies
Work EnvironmentInternship setting, supervised, focused on learning and assisting in RTL design tasksFull-time role, focused on testing and verifying RTL designs
Industry UsageUsed in semiconductor and chip design companies during early career stagesCommon in companies developing complex integrated circuits and chips

The Internship Asic Rtl Design Engineer focuses on assisting in RTL design tasks during an internship, emphasizing learning and support. In contrast, the Asic Verification Engineer is responsible for verifying RTL designs to ensure functionality. Both roles require similar educational backgrounds but differ in responsibilities and work environment, with verification roles being more advanced and permanent.

What are the most commonly searched types of Asic Rtl Design Engineer jobs in Seattle, WA? The most popular types of Asic Rtl Design Engineer jobs in Seattle, WA are:
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Internship Asic Rtl Design Engineer jobs near you
Infographic showing various Internship Asic Rtl Design Engineer job openings in Seattle, WA as of August 2026, with employment types broken down into 71% Full Time, and 29% Contract. Highlights an 67% In-person, and 33% Remote job distribution, with an average salary of $170,926 per year, or $82.2 per hour.

Senior ASIC Physical Design Engineer

K2 Space

Seattle, WA

$170K - $250K/yr

Full-time

Medical, Dental, Vision, Life, PTO

Re-posted 8 days ago

Job description

The Role 

We are seeking a Senior ASIC Physical Design Engineer to help implement advanced SoCs that power next-generation satellite and space systems. In this role, you will contribute to the full physical design flow-from synthesis to GDSII-working closely with architecture, RTL, verification, and packaging teams. You'll be a key contributor in achieving timing closure, optimizing PPA, and supporting design integration with external partners. You will be part of a collaborative design team developing state-of-the-art mixed-signal SoCs to be hosted on some of the largest, most powerful, rapidly designed and rapidly manufactured satellites ever deployed in space. In your first 6 months, you will develop and implement new SoC sub-systems for satellite communications and beyond. In your first two years, you will have contributed to developing cutting-edge SoCs that will fly in space. 

Responsibilities 

  • Execute the complete physical design flow for complex SoC blocks and top-level integration, including synthesis, floorplanning, place & route, CTS, STA, and physical verification. 
  • Perform timing closure and optimization across multiple corners and modes using industry-standard tools. 
  • Collaborate with front-end, verification, and DFT teams to ensure clean handoff and predictable convergence. 
  • Work with external physical design service providers and internal leads to review deliverables, resolve issues, and ensure schedule alignment. 
  • Develop and maintain scripts and automation to improve flow efficiency and consistency. 
  • Support physical sign-off activities including DRC/LVS, IR drop, EM, and power analysis. 
  • Assist in chip-level integration, ECOs, and tapeout preparation. 
  • Contribute to methodology development, tool evaluation, and flow documentation. 
  • Support your product through production and spaceflight.  

Required Qualifications 

  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field. 
  • 5-10 years of experience in ASIC physical design for complex SoCs. 
  • Hands-on experience with industry-standard tools (Synopsys ICC2/Fusion Compiler, Cadence Innovus, or equivalent). 
  • Strong understanding of timing analysis, power optimization, and physical verification flows. 
  • Experience with hierarchical or flat SoC design methodologies. 
  • Familiarity with FinFET technologies. 
  • Working knowledge of DFT, UPF/CPF power intent, and ECO implementation. 
  • Strong problem-solving skills and ability to work cross-functionally in fast-paced environments. 

Preferred Qualifications 

  • Exposure to radiation-hardened or space-qualified ASICs. 
  • Experience with chip-package co-design or advanced packaging (2.5D/3D). 
  • Familiarity with physical design service vendor management or offshore collaboration. 
  • Experience with sign-off through TSMC. 
  • Experience with Gate-All-Around technologies.  
  • Experience working in cross-functional, geographically distributed teams. 

Compensation and Benefits:

  • Base salary range for this role is $170,000 - $250,000 + equity in the company
  • Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
  • Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks
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About K2 Space

Sourced by ZipRecruiter

Industry

Guided missile and space vehicle manufacturing

Company size

11 - 50 Employees

Headquarters location

Los Angeles, CA, US

Year founded

2022

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