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Full Time Asic Rtl Design Engineer Jobs in Seattle, WA

FPGA Engineer, Amazon LEO OISL

Redmond, WA · On-site

$145K - $187K/yr

... RTL Design-Physical Implementation-Timing Closure-Simulation Validation- Lab Based Silicon ... with ASIC/FPGA design and verification tools - 3+ years of experience in ASIC/FPGA design ...

Craft micro-architecture specification, implement in high-quality RTL, and deliver a fully verified ... Deep understanding of ASIC design flows and methodology * Strong analytical and interpersonal ...

FPGA Engineer, Amazon LEO OISL

Redmond, WA · On-site

$145K - $187K/yr

... design engineer will work with systems teams to define/develop/implement/test/release FPGA based ... RTL Design-Physical Implementation-Timing Closure-Simulation Validation- Lab Based Silicon ...

FPGA Engineer, Amazon LEO OISL

Redmond, WA · On-site

$145K - $187K/yr

... design engineer will work with systems teams to define/develop/implement/test/release FPGA based ... RTL Design-Physical Implementation-Timing Closure-Simulation Validation- Lab Based Silicon ...

Sr. FPGA Engineer, Amazon Leo

Redmond, WA

$145K - $187K/yr

... ASIC design teams to support RTL development and verification - Mentor junior engineers and provide technical leadership on FPGA best practices - Work with cross-functional teams including system ...

Showing results 21-40

Full Time Asic Rtl Design Engineer information

See Seattle, WA salary details

$107K

$170.9K

$229.9K

How much do full time asic rtl design engineer jobs pay per year?

As of Aug 10, 2026, the average yearly pay for full time asic rtl design engineer in Seattle, WA is $170,926.00, according to ZipRecruiter salary data. Most workers in this role earn between $149,600.00 and $204,800.00 per year, depending on experience, location, and employer.

What is a full time ASIC RTL design engineer?

Full Time ASIC RTL Design Engineers are professionals who specialize in designing digital circuits at the Register Transfer Level (RTL) for Application Specific Integrated Circuits (ASICs). They use hardware description languages like Verilog or VHDL to create, simulate, and verify complex digital systems that are manufactured as custom chips. Their work typically involves collaborating with other engineers to optimize performance, area, and power consumption, as well as ensuring that the design meets specified requirements. These engineers play a crucial role in the development of chips used in various applications, including consumer electronics, automotive systems, and telecommunications.

How much does a full time ASIC RTL design engineer make?

A full-time ASIC RTL design engineer typically earns between $100,000 and $150,000 annually, depending on experience, location, and company size. Senior engineers with specialized skills in hardware description languages like Verilog or VHDL may earn higher salaries, often exceeding $160,000.

What are the key skills and qualifications needed to thrive as a full time ASIC RTL design engineer, and why are they important?

To thrive as a Full Time ASIC RTL Design Engineer, you need a solid background in digital logic design, computer architecture, and proficiency in Hardware Description Languages (HDLs) like Verilog or VHDL, typically supported by a degree in electrical or computer engineering. Familiarity with EDA tools such as Synopsys, Cadence, or Mentor Graphics, and knowledge of simulation, synthesis, and timing analysis, are crucial, with some roles requiring verification or DFT experience. Strong analytical thinking, attention to detail, and effective communication skills set exceptional engineers apart in team environments. These skills and qualities are essential for creating reliable, efficient hardware designs and ensuring successful silicon implementations in a competitive technology landscape.

Are full time ASIC RTL design engineers in demand?

Full-time ASIC RTL design engineers are in high demand due to the growth of semiconductor and electronics industries, requiring expertise in hardware description languages like Verilog and VHDL. Companies seek professionals skilled in RTL design, verification, and FPGA prototyping to develop advanced integrated circuits for various applications.

What are some common challenges full time ASIC RTL design engineers face when collaborating with verification teams?

A common challenge for ASIC RTL Design Engineers is ensuring that the design specifications are interpreted consistently between design and verification teams. Misalignment can lead to time-consuming bug fixes and delays in the project schedule. Effective communication, regular design reviews, and close collaboration are vital to catching issues early and maintaining project momentum. Additionally, engineers must often adapt quickly to evolving requirements or last-minute changes, which requires flexibility and strong problem-solving skills.

What is the salary of a full time ASIC RTL design engineer?

The average salary for a full-time ASIC RTL design engineer typically ranges from $100,000 to $150,000 annually, depending on experience, location, and company size. Senior engineers with specialized skills in hardware description languages like Verilog or VHDL and experience with FPGA or ASIC design may earn higher compensation. Benefits often include performance bonuses, health insurance, and opportunities for professional development.
What are the most commonly searched types of Asic Rtl Design Engineer jobs in Seattle, WA? The most popular types of Asic Rtl Design Engineer jobs in Seattle, WA are:
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Infographic showing various Full Time Asic Rtl Design Engineer job openings in Seattle, WA as of August 2026, with employment types broken down into 1% Internship, 86% Full Time, 8% Part Time, and 5% Contract. Highlights an 86% Physical, 4% Hybrid, and 10% Remote job distribution, with an average salary of $170,926 per year, or $82.2 per hour.

Senior ASIC Physical Design Engineer

K2 Space

Seattle, WA

$170K - $250K/yr

Full-time

Re-posted 9 days ago


Job description

K2 is building the largest and highest-power satellites ever flown, unlocking performance levels previously out of reach across every orbit. Backed by $450M from leading investors including Altimeter Capital, Redpoint Ventures, T. Rowe Price, Lightspeed Venture Partners, Alpine Space Ventures, and others – with an additional $500M in signed contracts across commercial and US government customers – we're mass-producing the highest-power satellite platforms ever built for missions from LEO to deep space.

The rise of heavy-lift launch vehicles is shifting the industry from an era of mass constraint to one of mass abundance, and we believe this new era demands a fundamentally different class of spacecraft. Engineered to survive the harshest radiation environments and to fully capitalize on today's and tomorrow's massive rockets, K2 satellites deliver unmatched capability at constellation scale and across multiple orbits.

With multiple launches planned through 2026 and 2027, we're Building Bigger to develop the solar system and become a Kardashev Type II (K2) civilization. If you are a motivated individual who thrives in a fast-paced environment and you're excited about contributing to the success of a groundbreaking Series C space startup, we'd love for you to apply.

The Role

We are seeking a Senior ASIC Physical Design Engineer to help implement advanced SoCs that power next-generation satellite and space systems. In this role, you will contribute to the full physical design flow—from synthesis to GDSII—working closely with architecture, RTL, verification, and packaging teams. You'll be a key contributor in achieving timing closure, optimizing PPA, and supporting design integration with external partners. You will be part of a collaborative design team developing state-of-the-art mixed-signal SoCs to be hosted on some of the largest, most powerful, rapidly designed and rapidly manufactured satellites ever deployed in space. In your first 6 months, you will develop and implement new SoC sub-systems for satellite communications and beyond. In your first two years, you will have contributed to developing cutting-edge SoCs that will fly in space. 

Responsibilities

  • Execute the complete physical design flow for complex SoC blocks and top-level integration, including synthesis, floorplanning, place & route, CTS, STA, and physical verification.
  • Perform timing closure and optimization across multiple corners and modes using industry-standard tools.
  • Collaborate with front-end, verification, and DFT teams to ensure clean handoff and predictable convergence.
  • Work with external physical design service providers and internal leads to review deliverables, resolve issues, and ensure schedule alignment.
  • Develop and maintain scripts and automation to improve flow efficiency and consistency.
  • Support physical sign-off activities including DRC/LVS, IR drop, EM, and power analysis.
  • Assist in chip-level integration, ECOs, and tapeout preparation.
  • Contribute to methodology development, tool evaluation, and flow documentation.
  • Support your product through production and spaceflight.

Required Qualifications

  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.
  • 5–10 years of experience in ASIC physical design for complex SoCs.
  • Hands-on experience with industry-standard tools (Synopsys ICC2/Fusion Compiler, Cadence Innovus, or equivalent).
  • Strong understanding of timing analysis, power optimization, and physical verification flows.
  • Experience with hierarchical or flat SoC design methodologies.
  • Familiarity with FinFET technologies.
  • Working knowledge of DFT, UPF/CPF power intent, and ECO implementation.
  • Strong problem-solving skills and ability to work cross-functionally in fast-paced environments.

Preferred Qualifications

  • Exposure to radiation-hardened or space-qualified ASICs.
  • Experience with chip-package co-design or advanced packaging (2.5D/3D).
  • Familiarity with physical design service vendor management or offshore collaboration.
  • Experience with sign-off through TSMC.
  • Experience with Gate-All-Around technologies.
  • Experience working in cross-functional, geographically distributed teams.

Compensation and Benefits:

  • Base salary range for this role is $170,000 – $250,000 + equity in the company
  • Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
  • Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks

If you don't meet 100% of the preferred skills and experience, we encourage you to still apply! Building a spacecraft unlike any other requires a team unlike any other and non-traditional career twists and turns are encouraged!

If you need a reasonable accommodation as part of your application for employment or interviews with us, please let us know.

Export Compliance

As defined in the ITAR, "U.S. Persons" include U.S. citizens, lawful permanent residents (i.e., Green Card holders), and certain protected individuals (e.g., refugees/asylees, American Samoans). Please consult with a knowledgeable advisor if you are unsure whether you are a "U.S. Person."

The person hired for this role will have access to information and items controlled by U.S. export control regulations, including the export control regulations outlined in the International Traffic in Arms Regulation (ITAR). The person hired for this role must therefore either be a "U.S. person" as defined by 22 C.F.R. § 120.15 or otherwise eligible for a federally issued export control license.

Equal Opportunity

K2 Space is an Equal Opportunity Employer; employment with K2 Space is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.


K2 Space logo

About K2 Space

Sourced by ZipRecruiter

Industry

Guided missile and space vehicle manufacturing

Company size

11 - 50 Employees

Headquarters location

Los Angeles, CA, US

Year founded

2022