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Fpga Uvm Verification Engineer Jobs (NOW HIRING)

Slope

FPGA Verification Engineer

Waltham, MA · On-site

$166 - $220/hr

Verification environment architecture and design using tools like SystemVerilog or OVM/UVM ... ASIC / FPGA verification flow * Contribute to engineering estimates for new program pursuits.

Altera

Senior Debug Verification Engineer

San Jose, CA

$149K - $215K/yr

About the Role As a Sr. Debug Design Verification Engineer , you will be responsible for Design for ... This include SoC, FPGA & Full Chip design verification. * Create testcase and testbench with UVM ...

Correct Designs

Design Verification Engineer

Austin, TX · On-site

$134K - $164K/yr

Correct Designs is currently seeking talented Verification Engineers with prior System Verilog UVM experience to work with our major clients both in Austin, TX, and nationwide. Opportunities span ...

RennickBarrett Recruiting, INC

FPGA Engineer

Cincinnati, OH · On-site

$124K - $160K/yr

The primary responsibilities will focus on Verilog FPGA design, System Verilog UVM verification and ... Programming experience in C for embedded systems, including development of algorithms, manipulation ...

Correct Designs

Design Verification Engineer

Austin, TX · On-site

$134K - $164K/yr

Correct Designs is currently seeking talented Verification Engineers with prior System Verilog UVM experience to work with our major clients both in Austin, TX, and nationwide. Opportunities span ...

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Fpga Uvm Verification Engineer information

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$80K

$142.6K

$203.5K

How much do fpga uvm verification engineer jobs pay per year?

As of Sep 6, 2026, the average yearly pay for fpga uvm verification engineer in the United States is $142,619.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $136,000.00 per year, depending on experience, location, and employer.

What is an FPGA UVM Verification Engineer?

FPGA UVM Verification Engineers are specialized professionals who verify and validate the functionality of Field Programmable Gate Arrays (FPGAs) using the Universal Verification Methodology (UVM). Their role involves creating testbenches and simulation environments to ensure that FPGA designs meet their specifications and operate reliably. They use hardware description languages like Verilog or VHDL and apply advanced verification techniques to identify and resolve design issues early in the development process. Their expertise is crucial for delivering high-quality, error-free FPGA products for applications in industries such as telecommunications, automotive, and aerospace.

What are the key skills and qualifications needed to thrive as an FPGA UVM Verification Engineer?

To excel as an FPGA UVM Verification Engineer, you need a solid background in digital design, verification methodologies, and a degree in electrical or computer engineering. Expertise with SystemVerilog, Universal Verification Methodology (UVM), and simulation tools like ModelSim or Questa is typically required. Strong analytical thinking, attention to detail, and effective communication are crucial soft skills that set top candidates apart. These skills ensure accurate and efficient verification of complex FPGA designs, leading to robust and reliable hardware products.

What are some common challenges faced by FPGA UVM Verification Engineers during project cycles?

FPGA UVM Verification Engineers often encounter challenges such as meeting tight verification deadlines, adapting to evolving specifications, and debugging complex functional issues in large-scale designs. Collaboration with design engineers is critical to resolve ambiguities and ensure comprehensive test coverage. Staying up-to-date with the latest UVM methodologies and maintaining reusable verification environments are also key aspects that require continuous learning and adaptability.

What is the difference between Fpga Uvm Verification Engineer vs FPGA Verification Engineer?

AspectFpga Uvm Verification EngineerFPGA Verification Engineer
Primary FocusUVM-based verification of FPGA designsGeneral FPGA design and verification
Skills & CertificationsUVM, SystemVerilog, FPGA toolsVerilog/VHDL, FPGA tools, verification skills
Work EnvironmentVerification teams, simulation environmentsDesign and verification teams, FPGA labs
Industry UsageHigh in verification-heavy projectsBroad, including design and verification

The Fpga Uvm Verification Engineer specializes in UVM-based verification methodologies for FPGA designs, focusing on creating testbenches and simulation environments. In contrast, the FPGA Verification Engineer may handle broader verification tasks, including both design and testing. Both roles require knowledge of FPGA tools and verification languages, but the UVM Verification Engineer emphasizes UVM and SystemVerilog expertise for verification processes.

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Fpga Uvm Verification Engineer jobs near you
Infographic showing various Fpga Uvm Verification Engineer job openings in the United States as of August 2026, with employment types broken down into 93% Full Time, 3% Part Time, and 4% Contract. Highlights an 86% Physical, 5% Hybrid, and 9% Remote job distribution, with an average salary of $142,619 per year, or $68.6 per hour.

FPGA Verification Engineer

Slope

Waltham, MA • On-site

$166 - $220/hr

Other

Posted 18 days ago

Key responsibilities

  • Design and develop verification environments and testbenches for RTL blocks using VHDL or SystemVerilog.

  • Create and execute test plans, test cases, and track code and functional coverage to verify FPGA designs.

  • Collaborate with interdisciplinary teams to define, analyze, and mature FPGA prototypes into products.

Job description

ABOUT THE TEAM

Anduril Imaging team develops state-of-the-art imaging systems across both hardware and software, deployed to tackle the most significant security challenges of America and its allies. The team is heavily involved in utilizing computer vision, perception, electro-optical, infrared, and sensor data to give our war fighters and allies an advantage.

ABOUT THE JOB

The Imaging team is seeking a FPGA Verification Engineer to help design a new product lines. In this role, you will work closely with an interdisciplinary technical team to define, complete the design and analysis, build prototypes leading to ground and flight testing, and mature the prototypes into products.

WHAT YOU’LL DO
  • Verification environment architecture and design using tools like SystemVerilog or OVM/UVM
  • Creation of written test plan, testcases, code coverage tracking, and functional coverage tracking
  • Testbench development for the verification of RTL blocks using VHDL or SystemVerilog
  • Recommend new tools and practices for continuous improvement in the group's ASIC / FPGA verification flow
  • Contribute to engineering estimates for new program pursuits.
  • Provide technical leadership for project verification teams by breaking down work, planning activities, and reporting status
REQUIRED QUALIFICATIONS
  • A Bachelor's in Electrical Engineering, Computer Engineering, or a related technical field is typically required.
  • 8+ years of experience developing HDL firmware for FPGA devices
  • Demonstrated experience developing and simulating RTL designs using VHDL and/or Verilog in a professional FPGA or ASIC development environment.
  • experience developing and simulating RTL designs using VHDL and/or Verilog in a professional FPGA or ASIC development environment.
  • Proven ability to design, implement, and execute verification testbenches for RTL blocks using VHDL and/or SystemVerilog.
  • experience applying chip-level verification methodologies, including constrained-random testing, functional coverage analysis, and assertion-based verification (SystemVerilog)
  • Experience using revision control systems such as Git or Subversion to manage source code, collaborate across engineering teams, and maintain configuration integrity.
  • Eligible to obtain and maintain an active U.S. Secret security clearance
PREFERRED QUALIFICATIONS
  • Experience with ASIC/FPGA lab validation and debug using standard lab equipment, along with familiarity with DFT, manufacturability, and production test concepts.
  • Proficiency with Unix/Linux environments, scripting or software development (C, C++, Python, Perl, or shell), and industry-standard ASIC/FPGA simulation and synthesis tools such as QuestaSim, Synplify, Quartus, or Vivado.

$166,000 — $220,000 USD

The salary range for this role is an estimate based on a wide range of compensation factors, inclusive of base salary only. Actual salary offer may vary based on (but not limited to) work experience, education and/or training, critical skills, and/or business considerations. Highly competitive equity grants are included in the majority of full time offers; and are considered part of Anduril's total compensation package. Additionally, Anduril offers top-tier benefits for full-time employees, including:

Benefits

At Anduril, we invest in our people. Our comprehensive, competitive benefits package (available at little to no cost to employees) ensures you’re supported in health, recovery, and whatever comes next. For more information, Explore Our Benefits.

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