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Fpga Uvm Verification Engineer Jobs in Reston, VA

Trident Systems LLC

Senior FPGA Engineer

Fairfax, VA · On-site

$97K - $181K/yr

Senior FPGA Engineer Requisition ID: 1806 Position Location: Fairfax, VA Position Reports To ... Experience using simulation verification libraries such as UVVM, UVM, OVM, etc. * Familiarity with ...

EndoSec LLC

FPGA Engineer

Reston, VA · On-site

$135K - $173K/yr

Use simulation tools and verification frameworks to ensure mathematically-correct logic before hardware deployment. Hardware/Software Design: Work closely with other engineers to integrate FPGA ...

EndoSec LLC

FPGA Engineer

Herndon, VA

$133K - $171K/yr

Use simulation tools and verification frameworks to ensure mathematically-correct logic before hardware deployment. Hardware/Software Design: Work closely with other engineers to integrate FPGA ...

Lynk

Senior FPGA_AIE Engineer

Chantilly, VA · On-site

$107K - $146K/yr

... verification, and validation. Core Responsibilities As a Senior FPGA_AIE Engineer, your core ... Experience with UVM or hardware in the loop testing methodologies. * Experience with RFICs and ...

BAE Systems

Eng Sr Prin II - Elec

Chantilly, VA · On-site

$149K - $254K/yr

The Engineering, Science and Analysis (ESA) Strategic Capabilities Unit comprises the technical ... Demonstrated technical leadership skills in FPGA design. * Experience with OVM/UVM Verification ...

BAE Systems

Eng Sr Prin - Elec

Chantilly, VA · On-site

$132K - $226K/yr

The Engineering, Science and Analysis (ESA) Strategic Capabilities Unit comprises the technical ... Demonstrated technical leadership skills in FPGA design. * Experience with OVM/UVM Verification ...

BAE Systems

Eng Sr Prin - Elec

Chantilly, VA · On-site

$132K - $226K/yr

The Engineering, Science and Analysis (ESA) Strategic Capabilities Unit comprises the technical ... Demonstrated technical leadership skills in FPGA design. * Experience with OVM/UVM Verification ...

iDirect GOVERNMENT

Senior FPGA Engineer

Herndon, VA · On-site

$91K - $159K/yr

Demonstrated ability to verify digital logic designs with System Verilog * Demonstrated ... FPGA and software design recommendations * Comfort working closely with HW/RF engineering ...

iDirect GOVERNMENT

Senior FPGA Engineer

Herndon, VA

$91K - $159K/yr

Demonstrated ability to verify digital logic designs with System Verilog * Demonstrated ... FPGA and software design recommendations * Comfort working closely with HW/RF engineering ...

Booz Allen Hamilton, Inc.

Embedded FPGA Engineer

Mclean, VA · On-site

$131K - $168K/yr

Embedded FPGA Engineer The Opportunity: We are seeking a motivated FPGA, and software engineer to ... Test, verify, and validate FPGA designs, ensuring functional correctness, stability, and ...

BAE Systems

Eng Prin - Elec

Chantilly, VA · On-site

$118K - $200K/yr

The Engineering, Science and Analysis (ESA) Strategic Capabilities Unit comprises the technical ... Demonstrated technical leadership skills in FPGA design. * Experience with OVM/UVM Verification ...

BAE Systems

Eng Prin - Elec

Chantilly, VA · On-site

$118K - $200K/yr

The Engineering, Science and Analysis (ESA) Strategic Capabilities Unit comprises the technical ... Demonstrated technical leadership skills in FPGA design. * Experience with OVM/UVM Verification ...

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All JobsFpga Uvm Verification Engineer JobsFpga Uvm Verification Engineer Jobs in Reston, VA

Fpga Uvm Verification Engineer information

See Reston, VA salary details

$83.2K

$148.4K

$211.7K

How much do fpga uvm verification engineer jobs pay per year?

As of Jul 31, 2026, the average yearly pay for fpga uvm verification engineer in Reston, VA is $148,375.00, according to ZipRecruiter salary data. Most workers in this role earn between $141,500.00 and $141,500.00 per year, depending on experience, location, and employer.

What are some common challenges faced by FPGA UVM Verification Engineers during project cycles?

FPGA UVM Verification Engineers often encounter challenges such as meeting tight verification deadlines, adapting to evolving specifications, and debugging complex functional issues in large-scale designs. Collaboration with design engineers is critical to resolve ambiguities and ensure comprehensive test coverage. Staying up-to-date with the latest UVM methodologies and maintaining reusable verification environments are also key aspects that require continuous learning and adaptability.

What are FPGA UVM Verification Engineers?

FPGA UVM Verification Engineers are specialized professionals who verify and validate the functionality of Field Programmable Gate Arrays (FPGAs) using the Universal Verification Methodology (UVM). Their role involves creating testbenches and simulation environments to ensure that FPGA designs meet their specifications and operate reliably. They use hardware description languages like Verilog or VHDL and apply advanced verification techniques to identify and resolve design issues early in the development process. Their expertise is crucial for delivering high-quality, error-free FPGA products for applications in industries such as telecommunications, automotive, and aerospace.

What is the difference between Fpga Uvm Verification Engineer vs FPGA Verification Engineer?

AspectFpga Uvm Verification EngineerFPGA Verification Engineer
Primary FocusUVM-based verification of FPGA designsGeneral FPGA design and verification
Skills & CertificationsUVM, SystemVerilog, FPGA toolsVerilog/VHDL, FPGA tools, verification skills
Work EnvironmentVerification teams, simulation environmentsDesign and verification teams, FPGA labs
Industry UsageHigh in verification-heavy projectsBroad, including design and verification

The Fpga Uvm Verification Engineer specializes in UVM-based verification methodologies for FPGA designs, focusing on creating testbenches and simulation environments. In contrast, the FPGA Verification Engineer may handle broader verification tasks, including both design and testing. Both roles require knowledge of FPGA tools and verification languages, but the UVM Verification Engineer emphasizes UVM and SystemVerilog expertise for verification processes.

What are the key skills and qualifications needed to thrive as an FPGA UVM Verification Engineer, and why are they important?

To excel as an FPGA UVM Verification Engineer, you need a solid background in digital design, verification methodologies, and a degree in electrical or computer engineering. Expertise with SystemVerilog, Universal Verification Methodology (UVM), and simulation tools like ModelSim or Questa is typically required. Strong analytical thinking, attention to detail, and effective communication are crucial soft skills that set top candidates apart. These skills ensure accurate and efficient verification of complex FPGA designs, leading to robust and reliable hardware products.
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Fpga Uvm Verification Engineer jobs near you
Infographic showing various Fpga Uvm Verification Engineer job openings in Reston, VA as of July 2026, with employment types broken down into 94% Full Time, 3% Part Time, and 3% Contract. Highlights an 88% Physical, 5% Hybrid, and 7% Remote job distribution, with an average salary of $148,375 per year, or $71.3 per hour.

FPGA Verification Engineer with Security Clearance

Legacy Consulting Services , LLC

Arlington, VA • On-site

$141K - $195K/yr

Other

Re-posted 10 hours ago

Job description

Location: Arlington, VA (HQ2) or Jessup, MD Clearance: Active TS/SCI with polygraph required Citizenship: US Citizen required Scope of Work
Develop and execute verification strategies for FPGA-based systems supporting AWS infrastructure. The contractor will build UVM-based verification environments, develop testbenches, and drive coverage closure for 100G+ networking solutions on advanced FPGA platforms. Key Responsibilities
• Develop UVM/SystemVerilog verification environments and testbenches for FPGA designs
• Create and execute verification plans with functional coverage models and assertions
• Drive coverage closure to completion (functional, code, and assertion coverage)
• Debug RTL failures in simulation and on hardware targets
• Develop constrained-random and directed test sequences for protocol verification (e.g., AXI, Ethernet)
• Perform regression analysis and coverage gap identification
• Collaborate with design engineers on architecture reviews and interface specifications
• Support hardware bring-up and debug on FPGA targets Required Qualifications
• BS in Electrical Engineering or related field
• 5+ years FPGA/ASIC verification experience
• SystemVerilog required
• 5+ years with UVM-based verification (constrained-random, coverage-driven methodologies)
• Demonstrated experience driving coverage closure to completion
• Strong UVM testbench architecture skills (agents, sequences, scoreboards, coverage models)
• Proficiency in SystemVerilog assertions (SVA) and simulation tools (Synopsys VCS, Mentor Questa, or equivalent)
• Experience verifying high-speed networking or datapath designs
• Knowledge of standard bus protocols (AXI, AXI-Stream, Ethernet)
• Active TS/SCI with polygraph (US Citizen)

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