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Engineer Cadence Jobs (NOW HIRING)

AI Engineer

San Jose, CA

$101.50K - $188.50K/yr

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of ... We are looking for a passionate software developer to join Virtuoso place and route infrastructure ...

Software Intern

San Jose, CA

$31.63 - $58.75/hr

Cadence is searching for a Software Engineer to work on delay calculation and signal integrity (SI) analysis in Static Timing Analysis tool. Responsible for implementing and extending existing ...

Software Intern

San Jose, CA · On-site

$31.63 - $58.75/hr

Cadence is searching for a Software Engineer to work on delay calculation and signal integrity (SI) analysis in Static Timing Analysis tool. Responsible for implementing and extending existing ...

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Engineer Cadence information

What is the difference between Engineer Cadence vs Engineer Test?

AspectEngineer CadenceEngineer Test
Required CredentialsBachelor's in Engineering, relevant certificationsBachelor's in Engineering, testing certifications often preferred
Work EnvironmentDesign, development, and implementation of hardware/softwareTesting, validation, and quality assurance of products
Industry UsageElectronics, semiconductor, software industriesElectronics, semiconductor, software industries

Engineer Cadence and Engineer Test roles often overlap in tech industries, but Cadence focuses on design and development, while Test emphasizes validation and quality assurance. Both roles require engineering backgrounds and are integral to product lifecycle stages.

More about Engineer Cadence jobs
What cities are hiring for Engineer Cadence jobs? Cities with the most Engineer Cadence job openings:
What states have the most Engineer Cadence jobs? States with the most job openings for Engineer Cadence jobs include:
Infographic showing various Engineer Cadence job openings in the United States as of May 2026, with employment types broken down into 75% Full Time, and 25% Contract. Highlights an 62% In-person, and 38% Remote job distribution.
Senior Principal Design Engineer

Senior Principal Design Engineer

Cadence Design Systems, Inc.

Austin, TX • On-site

Full-time

Posted 9 days ago


Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
The primary focus of Senior Principal Solutions Engineer is to support the adoption of Cadence Products to help Chip Designer Customers achieve superior performance for their Design PPA Goals. AE's are expected to possess Synthesis (logical and physical), Place and Route (primary focus) , STA / SDC skills and some experience supporting tapeouts. Experience with multivoltage design implementation and clock tree debugging is desirable.
In addition, Solutions Engineers are expected to be able to articulate design methodologies involving Cadence tools and be 'elevator talk' proficient in the full Cadence tool portfolio. Development time will be spent gaining expertise in additional, or specialization tools, broadening focus from product emphasis to methodology, Full Flow Implementation Training, and learning to leverage success . Full Flow Services Projects involves owning block implementation, top level implementation and Signoff focused efforts. Job exposure will be on RTL to GDSII delivery of projects. There's an opportunity to get involved in competitive benchmarking on complex blocks including CPUs, GPUs and DSP cores. These projects involve implementation in multiple technology nodes on standard foundry solutions. If you are looking to gain experience in methodology, product delivery, and working on cutting edge technology, this is the right role for you.
Position Requirements:
* Design experience should include ASIC design using industry-standard hardware description languages (Verilog)
* Senior Level Applications Engineer position with Deep Cadence or Synopsys place and route tool knowledge (Physical Synthesis, PnR, CTS, Static Timing Analysis) experience and knowledge are required
* Innovate with Low Power and Multi-Voltage Design Techniques working with leading edge Wireless and Mobile Customers
* Senior level Design Engineer position supporting RTL-to-GDS implementation flows using Encounter Digitial Implementation Platform
* Manage strategic customer evaluations/benchmarks on Cadence's front-end solutions to establish technology differentiation and assert Cadence competitive advantages. Multiplex several issues and set priorities and exploit new technologies are essential for success in the position
* Assist customers with adopting Cadence Front End tools in Synthesis with Genus DFT & Scan with Encounter Test (ET) by providing methodology and tool knowledge to IC design process, validated through successful design tapeouts
* Drive best practices and lessons learnt from evaluations/benchmarks and customer interactions back in to product development and Cadence field engineers. Develop an understanding of the customer's needs and also of the competition's technology and sales strategies
* Support regional customers and support major level customer (50% plus support) in the local region
* Perform methodology assessments, improve existing design methodologies, and develop new ones that leverage Cadence technology and services.
* Assists sales staff in assessing potential application of company product to meet customer needs and preparing detailed product specifications.
* Create and conduct technical presentations and product demonstrations to customers
* Some TCL/Perl Scripting will be expected to achieve quick Design Automation solutions for customer
The Position Requirements are... Normally requires a BS degree & 7 years experience and a strong technical knowledge of company products.
NOT AN ENTRY LEVEL POSITION
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