... verification team in test bench development, formal methods, and simulation/emulation for ... a CPU microarchitecture Experience in C or C++ programming Experience using an interpretive ...
... verification team in test bench development, formal methods, and simulation/emulation for ... a CPU microarchitecture Experience in C or C++ programming Experience using an interpretive ...
CPU Cache Microarchitect/RTL Engineer
$184K - $324K/yr
Medical
Dental
Retirement
... verification team in test bench development, formal methods, and simulation/emulation for ... a CPU microarchitecture Experience in C or C++ programming Experience using an interpretive ...
CPU Cache Microarchitect/RTL Engineer
$184K - $324K/yr
Medical
Dental
Retirement
... verification team in test bench development, formal methods, and simulation/emulation for ... a CPU microarchitecture Experience in C or C++ programming Experience using an interpretive ...
... verification team in test bench development, formal methods, and simulation/emulation for ... a CPU microarchitecture Experience in C or C++ programming Experience using an interpretive ...
... verification team in test bench development, formal methods, and simulation/emulation for ... a CPU microarchitecture Experience in C or C++ programming Experience using an interpretive ...
CPU Cache Microarchitect/RTL Engineer
$184K - $324K/yr
Medical
Dental
Retirement
... verification team in test bench development, formal methods, and simulation/emulation for ... a CPU microarchitecture Experience in C or C++ programming Experience using an interpretive ...
CPU Cache Microarchitect/RTL Engineer
$184K - $324K/yr
Medical
Dental
Retirement
... verification team in test bench development, formal methods, and simulation/emulation for ... a CPU microarchitecture Experience in C or C++ programming Experience using an interpretive ...
... verification team in test bench development, formal methods, and simulation/emulation for ... a CPU microarchitecture Experience in C or C++ programming Experience using an interpretive ...
... verification team in test bench development, formal methods, and simulation/emulation for ... a CPU microarchitecture Experience in C or C++ programming Experience using an interpretive ...
CPU Cache Microarchitect/RTL Engineer
$184K - $324K/yr
Medical
Dental
Retirement
... verification team in test bench development, formal methods, and simulation/emulation for ... a CPU microarchitecture Experience in C or C++ programming Experience using an interpretive ...
CPU Cache Microarchitect/RTL Engineer
$184K - $324K/yr
Medical
Dental
Retirement
... verification team in test bench development, formal methods, and simulation/emulation for ... a CPU microarchitecture Experience in C or C++ programming Experience using an interpretive ...
Senior CPU RTL Design Engineer
Hillsboro, OR · On-site
Medical
Retirement
PTO
As a CPU RTL Logic Design Engineer your responsibilities will include but are not limited to ... Reviews the verification plan and implementation to ensure design features are verified correctly ...
Senior CPU RTL Design Engineer
Hillsboro, OR · On-site
Medical
Retirement
PTO
As a CPU RTL Logic Design Engineer your responsibilities will include but are not limited to ... Reviews the verification plan and implementation to ensure design features are verified correctly ...
CPU Cache Microarchitect/RTL Engineer
$184K - $324K/yr
Medical
Dental
Retirement
... verification team in test bench development, formal methods, and simulation/emulation for ... a CPU microarchitecture Experience in C or C++ programming Experience using an interpretive ...
CPU Cache Microarchitect/RTL Engineer
$184K - $324K/yr
Medical
Dental
Retirement
... verification team in test bench development, formal methods, and simulation/emulation for ... a CPU microarchitecture Experience in C or C++ programming Experience using an interpretive ...
CPU Cache Microarchitect/RTL Engineer
$184K - $324K/yr
Medical
Dental
Retirement
... verification team in test bench development, formal methods, and simulation/emulation for ... a CPU microarchitecture Experience in C or C++ programming Experience using an interpretive ...
CPU Cache Microarchitect/RTL Engineer
$184K - $324K/yr
Medical
Dental
Retirement
... verification team in test bench development, formal methods, and simulation/emulation for ... a CPU microarchitecture Experience in C or C++ programming Experience using an interpretive ...
... verification team in test bench development, formal methods, and simulation/emulation for ... a CPU microarchitecture Experience in C or C++ programming Experience using an interpretive ...
... verification team in test bench development, formal methods, and simulation/emulation for ... a CPU microarchitecture Experience in C or C++ programming Experience using an interpretive ...
CPU Cache Microarchitect/RTL Engineer
$184K - $324K/yr
Medical
Dental
Retirement
... verification team in test bench development, formal methods, and simulation/emulation for ... a CPU microarchitecture Experience in C or C++ programming Experience using an interpretive ...
CPU Cache Microarchitect/RTL Engineer
$184K - $324K/yr
Medical
Dental
Retirement
... verification team in test bench development, formal methods, and simulation/emulation for ... a CPU microarchitecture Experience in C or C++ programming Experience using an interpretive ...
Senior CPU RTL Design Engineer
Hillsboro, OR · On-site
Medical
Retirement
PTO
As a CPU RTL Logic Design Engineer your responsibilities will include but are not limited to ... Reviews the verification plan and implementation to ensure design features are verified correctly ...
Senior CPU RTL Design Engineer
Hillsboro, OR · On-site
Medical
Retirement
PTO
As a CPU RTL Logic Design Engineer your responsibilities will include but are not limited to ... Reviews the verification plan and implementation to ensure design features are verified correctly ...
CPU Design Timing Engineer
$184K - $324K/yr
Medical
Dental
Retirement
... verification is a plus Possess data parsing, analysis and representation/plotting skills Minimum Qualifications Minimum BS and 10+ years of relevant experience Experience with a static timing ...
CPU Design Timing Engineer
$184K - $324K/yr
Medical
Dental
Retirement
... verification is a plus Possess data parsing, analysis and representation/plotting skills Minimum Qualifications Minimum BS and 10+ years of relevant experience Experience with a static timing ...
Mid-level Physical Design Engineer CPU
Hillsboro, OR · On-site
$148K - $152K/yr
Medical
Retirement
PTO
As a Mid-level Physical Design Engineer CPU, you will contribute to delivering high-performance ... Collaborate with RTL design, verification, clocking, and full-chip teams * Support improvements to ...
Mid-level Physical Design Engineer CPU
Hillsboro, OR · On-site
$148K - $152K/yr
Medical
Retirement
PTO
As a Mid-level Physical Design Engineer CPU, you will contribute to delivering high-performance ... Collaborate with RTL design, verification, clocking, and full-chip teams * Support improvements to ...
CPU Design Timing Engineer
$184K - $324K/yr
Medical
Dental
Retirement
... verification is a plus Possess data parsing, analysis and representation/plotting skills Minimum Qualifications Minimum BS and 10+ years of relevant experience Experience with a static timing ...
CPU Design Timing Engineer
$184K - $324K/yr
Medical
Dental
Retirement
... verification is a plus Possess data parsing, analysis and representation/plotting skills Minimum Qualifications Minimum BS and 10+ years of relevant experience Experience with a static timing ...
CPU Physical Design Engineer
$184K - $324K/yr
Medical
Dental
Retirement
Apple's Silicon Engineering Group (SEG) is hiring hardworking engineers for CPU block-level ... verification to converge complex designs Knowledge in deep sub-micron technology, along with its ...
CPU Physical Design Engineer
$184K - $324K/yr
Medical
Dental
Retirement
Apple's Silicon Engineering Group (SEG) is hiring hardworking engineers for CPU block-level ... verification to converge complex designs Knowledge in deep sub-micron technology, along with its ...
CPU Design Timing Engineer
$184K - $324K/yr
Medical
Dental
Retirement
... verification is a plus Possess data parsing, analysis and representation/plotting skills Minimum Qualifications Minimum BS and 10+ years of relevant experience Experience with a static timing ...
CPU Design Timing Engineer
$184K - $324K/yr
Medical
Dental
Retirement
... verification is a plus Possess data parsing, analysis and representation/plotting skills Minimum Qualifications Minimum BS and 10+ years of relevant experience Experience with a static timing ...
... verification team in test bench development, formal methods, and simulation/emulation for ... a CPU microarchitecture Experience in C or C++ programming Experience using an interpretive ...
... verification team in test bench development, formal methods, and simulation/emulation for ... a CPU microarchitecture Experience in C or C++ programming Experience using an interpretive ...
CPU Physical Design Engineer
$184K - $324K/yr
Medical
Dental
Retirement
Apple's Silicon Engineering Group (SEG) is hiring hardworking engineers for CPU block-level ... verification to converge complex designs Knowledge in deep sub-micron technology, along with its ...
CPU Physical Design Engineer
$184K - $324K/yr
Medical
Dental
Retirement
Apple's Silicon Engineering Group (SEG) is hiring hardworking engineers for CPU block-level ... verification to converge complex designs Knowledge in deep sub-micron technology, along with its ...
... verification team in test bench development, formal methods, and simulation/emulation for ... a CPU microarchitecture Experience in C or C++ programming Experience using an interpretive ...
... verification team in test bench development, formal methods, and simulation/emulation for ... a CPU microarchitecture Experience in C or C++ programming Experience using an interpretive ...
Cpu Verification Engineer information
See Oregon salary details
$84.6K - $96.5K
1% of jobs
$96.5K - $108.3K
1% of jobs
$108.3K - $120.2K
1% of jobs
$120.2K - $132.1K
1% of jobs
$139.1K is the 25th percentile. Wages below this are outliers.
$132.1K - $143.9K
35% of jobs
The median wage is $146.3K / yr.
$143.9K - $155.8K
54% of jobs
$155.8K - $167.7K
1% of jobs
$167.7K - $179.5K
1% of jobs
$179.5K - $191.4K
2% of jobs
$191.4K - $203.3K
1% of jobs
$203.3K - $215.2K
1% of jobs
$84.6K
$150.8K
$215.2K
How much do cpu verification engineer jobs pay per year?
As of Aug 16, 2026, the average yearly pay for cpu verification engineer in Oregon is $150,789.00, according to ZipRecruiter salary data. Most workers in this role earn between $143,800.00 and $143,800.00 per year, depending on experience, location, and employer.
What is a CPU verification engineer?
A CPU Verification Engineer is responsible for ensuring that a CPU design functions correctly before manufacturing. They develop and execute test plans using simulation, formal verification, and other methodologies to validate processor behavior against specifications. This role requires knowledge of hardware description languages (like Verilog or VHDL), verification languages (such as SystemVerilog UVM), and debugging tools. CPU Verification Engineers collaborate with architects and designers to identify and resolve design issues. Their work is critical in catching bugs early, improving performance, and ensuring the reliability of modern processors.
What are the key skills and qualifications needed to thrive in the CPU verification engineer position, and why are they important?
A CPU Verification Engineer requires a solid understanding of computer architecture, digital logic design, and verification methodologies, typically backed by a degree in electrical or computer engineering. Familiarity with hardware description languages (such as Verilog or VHDL), industry-standard verification tools (like UVM, SystemVerilog), and scripting languages is highly valued. Strong problem-solving abilities, attention to detail, and effective teamwork and communication skills help candidates excel in this role. These qualifications are essential to ensure rigorous testing of complex CPU designs, minimize costly errors, and drive project success.
What are the typical responsibilities of a CPU verification engineer during a project lifecycle?
As a CPU Verification Engineer, you'll work closely with design teams to develop and execute verification plans, write and maintain testbenches, and run simulations to uncover design issues. Your responsibilities will include identifying edge cases, debugging failures, ensuring coverage goals are met, and collaborating in code reviews. Projects often involve cross-functional teamwork with architects, design engineers, and software teams, offering exposure to various aspects of CPU development. This role is both technically demanding and highly collaborative, providing valuable opportunities to contribute to the creation of next-generation processors.
What are popular job titles related to Cpu Verification Engineer jobs in Oregon?
For Cpu Verification Engineer jobs in Oregon, the most frequently searched job titles are:
What job categories do people searching Cpu Verification Engineer jobs in Oregon look for?
The top searched job categories for Cpu Verification Engineer jobs in Oregon are:
What cities in Oregon are hiring for Cpu Verification Engineer jobs?
Cities in Oregon with the most Cpu Verification Engineer job openings:
Full-time
Re-posted 21 days ago
Apple rating
8.0
Based on 677 frontline employees who took The Breakroom Quiz
7th of 30 rated technology retailers
Job description
Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hard-working people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products! The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Do you want to join us in these pursuits? Join us to help deliver the next groundbreaking Apple product!
Apple's Silicon Engineering Group (SEG) designs high-performance, low power microprocessors that power our innovative products, including the iPhone, iPad, Watch, Vision Pro, and Mac. We are looking for an experienced engineer to help drive architecture and RTL for world-class CPU power management solutions.
Description
As a CPU RTL Architect, you will own or participate in the following:
• Micro-architecture development and specification - from early high-level architectural exploration, through micro-architectural research and arriving at a detailed specification
• RTL ownership - development, assessment and refinement of RTL design to target power, performance, area and timing goals
• Verification - support the verification team in test bench development, formal methods, and simulation/emulation for functional verification
• Performance exploration and correlation - explore high-performance strategies and work with the performance verification team to verify that the RTL design meets targeted performance
• Design delivery - work with multi-functional engineering team to implement and verify physical design on the aspects of timing, area, reliability, testability and power
Minimum Qualifications
Minimum BS and 10+ years of relevant industry experience
Experience with microprocessor architecture
Experience with logic design principles with timing and power implications
Experience in Verilog or VHDL
Experience with simulators and waveform debugging process
Preferred Qualifications
Expertise in one or more of the following areas: dynamic voltage and frequency scaling (DVFS/DVFM), advanced thermal and energy management, power state definition and management, dynamic clocking solutions, Di/dt mitigation strategies, micro-architecture strategies for improved power integrity, debug solutions, error handling, reset control, clock generation and asynchronous clock crossing strategies
Understanding of low power microarchitecture techniques
Understanding of high-performance techniques and trade-offs in a CPU microarchitecture
Experience in C or C++ programming
Experience using an interpretive language such as Perl or Python
Apple's Silicon Engineering Group (SEG) designs high-performance, low power microprocessors that power our innovative products, including the iPhone, iPad, Watch, Vision Pro, and Mac. We are looking for an experienced engineer to help drive architecture and RTL for world-class CPU power management solutions.
Description
As a CPU RTL Architect, you will own or participate in the following:
• Micro-architecture development and specification - from early high-level architectural exploration, through micro-architectural research and arriving at a detailed specification
• RTL ownership - development, assessment and refinement of RTL design to target power, performance, area and timing goals
• Verification - support the verification team in test bench development, formal methods, and simulation/emulation for functional verification
• Performance exploration and correlation - explore high-performance strategies and work with the performance verification team to verify that the RTL design meets targeted performance
• Design delivery - work with multi-functional engineering team to implement and verify physical design on the aspects of timing, area, reliability, testability and power
Minimum Qualifications
Minimum BS and 10+ years of relevant industry experience
Experience with microprocessor architecture
Experience with logic design principles with timing and power implications
Experience in Verilog or VHDL
Experience with simulators and waveform debugging process
Preferred Qualifications
Expertise in one or more of the following areas: dynamic voltage and frequency scaling (DVFS/DVFM), advanced thermal and energy management, power state definition and management, dynamic clocking solutions, Di/dt mitigation strategies, micro-architecture strategies for improved power integrity, debug solutions, error handling, reset control, clock generation and asynchronous clock crossing strategies
Understanding of low power microarchitecture techniques
Understanding of high-performance techniques and trade-offs in a CPU microarchitecture
Experience in C or C++ programming
Experience using an interpretive language such as Perl or Python
About Apple
Sourced by ZipRecruiter
Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it.
Industry
Computer and electronic product manufacturing
Company size
10,000+ Employees
Headquarters location
Cupertino, CA, US
Year founded
1976