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Contractual Asic Rtl Design Engineer Jobs in Berkeley, CA

Mixed-Signal Verification Engineer

San Francisco, CA · On-site

$160K - $195K/yr

All of which is driven by a world-class vertically integrated engineering team, spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration ...

Mixed-Signal Verification Engineer

San Francisco, CA · On-site

$160K - $195K/yr

All of which is driven by a world-class vertically integrated engineering team, spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration ...

FPGA Hardware Engineer

San Francisco, CA · On-site

$154K - $225K/yr

We design the networking hardware for Enterprises and Service Providers of various sizes, the ... FPGA or ASIC development experience from specification to production. * Experience with Verilog ...

Sr. RTL Verification Engineer

Redwood City, CA · On-site

$166K - $203K/yr

We are seeking a Sr. RTL Verification Engineer to join our team in Redwood City to bring the power of generative AI to enhance and speed the design and manufacture of complex semiconductors.

... and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. Description In this highly visible role, you will be at the center of a ...

As an Eliyan Principal Physical Design Engineer, you will be working at a fast-paced early-stage ... You will drive the development of cutting‑edge ASICs from RTL to GDSII. You will work with a ...

Software Engineer, ASIC

South San Francisco, CA · On-site

$199K/yr

As a Software Engineer, ASIC, you will integrate tightly with teams across the company, and span ... Build and maintain scalable EDA compute infrastructure for analog and digital chip design * Develop ...

Staff SoC RTL Engineer

Burlingame, CA · On-site

$175K - $230K/yr

As a Staff SoC RTL Engineer , you will get in on the ground floor as a key member of our chip ... Minimum 5+ years of hands-on SoC/ASIC front-end design and integration experience. * Proficiency in ...

Showing results 41-60

Contractual Asic Rtl Design Engineer information

See Berkeley, CA salary details

$115.1K

$183.9K

$247.3K

How much do contractual asic rtl design engineer jobs pay per year?

As of Aug 15, 2026, the average yearly pay for contractual asic rtl design engineer in Berkeley, CA is $183,905.00, according to ZipRecruiter salary data. Most workers in this role earn between $161,000.00 and $220,400.00 per year, depending on experience, location, and employer.

What is the difference between Contractual Asic Rtl Design Engineer vs Digital IC Design Engineer?

AspectContractual Asic Rtl Design EngineerDigital IC Design Engineer
CredentialsBachelor's/Master's in Electrical Engineering or Computer EngineeringBachelor's/Master's in Electrical Engineering or Computer Engineering
Work EnvironmentContract-based, project-specific, often in semiconductor or tech companiesFull-time or contract, working on digital integrated circuit design
Industry UsageCommon in semiconductor, electronics, and tech firms for ASIC developmentUsed across semiconductor, consumer electronics, and communication industries

Both roles require similar educational backgrounds and work in related environments, focusing on digital circuit design. The main difference is that Contractual Asic Rtl Design Engineers typically work on specific ASIC projects on a contractual basis, while Digital IC Design Engineers may have broader responsibilities in digital chip development, often in full-time roles.

What are the most commonly searched types of Asic Rtl Design Engineer jobs in Berkeley, CA?

The most popular types of Asic Rtl Design Engineer jobs in Berkeley, CA are:

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For Contractual Asic Rtl Design Engineer jobs in Berkeley, CA, the most frequently searched job titles are:

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The top searched job categories for Contractual Asic Rtl Design Engineer jobs in Berkeley, CA are:

What cities near Berkeley, CA are hiring for Contractual Asic Rtl Design Engineer jobs?

Cities near Berkeley, CA with the most Contractual Asic Rtl Design Engineer job openings:

Infographic showing various Contractual Asic Rtl Design Engineer job openings in Berkeley, CA as of August 2026, with employment types broken down into 94% Full Time, and 6% Part Time. Highlights an 89% In-person, and 11% Remote job distribution, with an average salary of $183,905 per year, or $88.4 per hour.

Software Engineer, ASIC

Neuralink

South San Francisco, CA • On-site

Full-time

Re-posted 25 days ago


Job description

Job Summary:
Neuralink is creating devices that enable a bi-directional interface with the brain, aiming to restore movement and sight while revolutionizing human interaction with the digital world. The Software Engineer, ASIC will integrate with teams across the company to build and maintain scalable EDA compute infrastructure and enhance developer experience for IC design and firmware engineers.
Responsibilities:
• Build and maintain scalable EDA compute infrastructure for analog and digital chip design
• Develop distributed simulation clusters to accelerate circuit verification at scale
• Manage and optimize license infrastructure across multiple EDA vendors
• Architect high-performance and robust shared storage for terabyte-scale design data
• Develop build-system infrastructure and tooling for firmware targeting custom ASICs
• Automate bare-metal server provisioning and lifecycle management for EDA compute fleets
• Enhance developer experience for IC design and firmware engineers through monitoring, self-service tooling, and robust automation
Qualifications:
Required:
• Experience administering EDA compute environments and toolchains (Cadence, Synopsys, Siemens/Mentor)
• Working knowledge of FlexLM license server administration and capacity management.
• Working knowledge of compiled languages, ideally Rust, Go, or C/C++.
• Experience with high-performance Linux storage: NFS, ZFS, Ceph, iSCSI, or similar.
• Systems administration experience on RHEL and Ubuntu, kernel tuning for compute workloads
• Familiarity with distributed compute frameworks (Ray, Slurm, LSF, or similar)
• Experience with bare-metal provisioning and lifecycle management at datacenter scale
• Familiarity with embedded cross-compilation toolchains and build systems (ARM, Bazel, Nix)
• Experience with multi-cloud deployments and hybrid on-prem/cloud architectures
• Bachelor's degree in computer science, a related field, or an equivalent combination of education, training, and/or experience
Company:
Neuralink is a neurotechnology company that focuses on developing brain-computer interfaces designed to treat neurological disorders. Founded in 2016, the company is headquartered in Fremont, USA, with a team of 201-500 employees. The company is currently Growth Stage.