1

Contractual Asic Rtl Design Engineer Jobs in Berkeley, CA

Connectivity Systems Engineer

San Francisco, CA · On-site

$117K - $161K/yr

All of this is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration ...

Physical Design Engineer

San Francisco, CA · On-site

$160K - $164K/yr

Description As a Physical Design engineer you will contribute to all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII. Minimum Qualifications Bachelors ...

Sr FPGA Design Engineer

San Francisco, CA

$144K - $199K/yr

Responsibilities Design, implement, and verify RTL solutions using VHDL, Verilog, and SystemVerilog ... Help maintain engineering excellence by sharing knowledge and providing guidance to teammates when ...

Physical Design Engineer

San Francisco, CA · On-site

$160K - $164K/yr

Description As a Physical Design engineer you will contribute to all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII. Your responsibilities include ...

Physical Design Engineer

San Francisco, CA · On-site

$160K - $164K/yr

Description As a Physical Design engineer you will contribute to all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII. Your responsibilities include ...

As an ASIC Engineer specializing in architecture, performance and modeling, you will define and ... Collaborate with cross functional teams working on RTL design, Design Verification, Firmware ...

Physical Design Engineer

San Francisco, CA · On-site

$160K - $164K/yr

Description As a Physical Design engineer you will contribute to all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII. Your responsibilities include ...

The engineer will work closely with ASIC, package, system, mechanical, thermal, power, and silicon ... Drive die/package co-design, including bump/BGA assignment, stack-up optimization, power/ground ...

MMIC Design Engineer

Menlo Park, CA · On-site +1

$160K - $250K/yr

We are seeking a highly experienced THz IC Design Engineer to join our growing team. In this role ... Understanding tradeoff at the device level for high performance ASIC implementation * Ability to ...

We are seeking a highly experienced THz IC Design Engineer to join our growing team. In this role ... Understanding tradeoff at the device level for high performance ASIC implementation * Ability to ...

The engineer will work closely with ASIC, package, system, mechanical, thermal, power, and silicon ... Drive die/package co-design, including bump/BGA assignment, stack-up optimization, power/ground ...

Sr FPGA Design Engineer

San Francisco, CA · On-site

$144K - $199K/yr

Design, implement, and verify RTL solutions using VHDL, Verilog, and SystemVerilog for FPGA IP blocks and subsystem-level functionality. * Develop, enhance, and execute functional testbenches to ...

Showing results 41-60

Contractual Asic Rtl Design Engineer information

See Berkeley, CA salary details

$115.1K

$183.9K

$247.3K

How much do contractual asic rtl design engineer jobs pay per year?

As of Sep 5, 2026, the average yearly pay for contractual asic rtl design engineer in Berkeley, CA is $183,905.00, according to ZipRecruiter salary data. Most workers in this role earn between $161,000.00 and $220,400.00 per year, depending on experience, location, and employer.

What is the difference between Contractual Asic Rtl Design Engineer vs Digital IC Design Engineer?

AspectContractual Asic Rtl Design EngineerDigital IC Design Engineer
CredentialsBachelor's/Master's in Electrical Engineering or Computer EngineeringBachelor's/Master's in Electrical Engineering or Computer Engineering
Work EnvironmentContract-based, project-specific, often in semiconductor or tech companiesFull-time or contract, working on digital integrated circuit design
Industry UsageCommon in semiconductor, electronics, and tech firms for ASIC developmentUsed across semiconductor, consumer electronics, and communication industries

Both roles require similar educational backgrounds and work in related environments, focusing on digital circuit design. The main difference is that Contractual Asic Rtl Design Engineers typically work on specific ASIC projects on a contractual basis, while Digital IC Design Engineers may have broader responsibilities in digital chip development, often in full-time roles.

What are the most commonly searched types of Asic Rtl Design Engineer jobs in Berkeley, CA?

The most popular types of Asic Rtl Design Engineer jobs in Berkeley, CA are:

What are popular job titles related to Contractual Asic Rtl Design Engineer jobs in Berkeley, CA?

For Contractual Asic Rtl Design Engineer jobs in Berkeley, CA, the most frequently searched job titles are:

What job categories do people searching Contractual Asic Rtl Design Engineer jobs in Berkeley, CA look for?

The top searched job categories for Contractual Asic Rtl Design Engineer jobs in Berkeley, CA are:

What cities near Berkeley, CA are hiring for Contractual Asic Rtl Design Engineer jobs?

Cities near Berkeley, CA with the most Contractual Asic Rtl Design Engineer job openings:

Infographic showing various Contractual Asic Rtl Design Engineer job openings in Berkeley, CA as of August 2026, with employment types broken down into 94% Full Time, and 6% Part Time. Highlights an 89% In-person, and 11% Remote job distribution, with an average salary of $183,905 per year, or $88.4 per hour.

Connectivity Systems Engineer

Apple

San Francisco, CA • On-site

$117K - $161K/yr

Full-time

Re-posted 24 days ago


Apple rating

8.1

Company rating: 8.1 out of 10

Based on 681 frontline employees who took The Breakroom Quiz

6th of 30 rated technology retailers


Job description

Come join Apple's growing wireless silicon development team. Our wireless SoC organization is responsible for all aspects of wireless silicon development, with a particular emphasis on highly energy-efficient design and new technologies that transform the user experience at the product level. All of this is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. In this role, you will help de-risk our silicon well ahead of tape-out by owning the pre-silicon emulation environment that enables the team to exercise and verify new designs early and with confidence. If you enjoy a fast-paced and challenging environment, collaborate with people across different functional areas, and thrive during crisis times, we encourage you to apply.
Description
This role is central to Apple's pre-silicon verification effort for wireless SoCs, centered on the Palladium emulation platform. You will be the first to bring up each newly released emulation build, and you will design and own the framework and infrastructure - register maps, initialization and boot sequences, clock and reset, and system-level configuration - that brings the emulated SoC into an operational state and enables the wider team to run their own design verification. Working at the intersection of digital design, firmware, and validation, you will own and evolve this infrastructure across successive silicon generations, while also contributing to pre-silicon emulation and lab bring-up of Bluetooth and UWB silicon.
Minimum Qualifications
Bachelor's degree with 10 years of relevant experience.
Strong digital design fundamentals with hands-on RTL experience (Verilog/VHDL) and a solid understanding of SoC architecture, register maps, and system-level hardware/software interaction.
Working knowledge of wireless systems, including MAC and/or PHY layer concepts.
Proficiency in Python and/or C/C++ for developing modeling, simulation, and test-bench/verification infrastructure.
Strong communication skills, both written and oral, with the ability to work effectively across cross-functional teams.
Preferred Qualifications
Master's degree with 10 years of relevant experience.
Hands-on experience with pre-silicon verification using emulation platforms (e.g., Palladium), including build bring-up, environment and framework development, debug, and performance characterization.
Experience developing verification or validation frameworks and infrastructure - including register map and programming-model definition, initialization sequences, clock and reset setup, and system-level configuration.
Digital design or design verification (DV) experience with wireless SoCs or subsystems, including RTL design or test-bench development and functional coverage.
Working knowledge of Bluetooth and UWB wireless systems, with hands-on experience in BT and UWB systems design and validation.
Experience collaborating with firmware and FPGA/emulation engineers to bring up, integrate, and debug the emulation platform, ensuring correct hardware/software interaction and a properly functioning environment.

What Apple employees say

Pay

Benefits

Hours and flexibility

Workplace

Get the full story on Breakroom


Apple logo

About Apple

Sourced by ZipRecruiter

Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it.

Industry

Computer and electronic product manufacturing

Company size

10,000+ Employees

Headquarters location

Cupertino, CA, US

Year founded

1976