The Software Engineer, ASIC will integrate with teams across the company to build and maintain ... design and firmware engineers. Responsibilities : • Build and maintain scalable EDA compute ...
The Software Engineer, ASIC will integrate with teams across the company to build and maintain ... design and firmware engineers. Responsibilities : • Build and maintain scalable EDA compute ...
Director, Product Engineering Practice Specialist (Semiconductor)
San Francisco, CA · On-site
$200K/yr
... ASIC/SoC Design Lifecycle • Architecture and Microarchitecture • RTL Design • Design ... Engineering and RTOS • FPGA Prototyping and Emulation • Synopsys, Cadence and Siemens EDA ...
Director, Product Engineering Practice Specialist (Semiconductor)
San Francisco, CA · On-site
$200K/yr
... ASIC/SoC Design Lifecycle • Architecture and Microarchitecture • RTL Design • Design ... Engineering and RTOS • FPGA Prototyping and Emulation • Synopsys, Cadence and Siemens EDA ...
Hardware Design Engineer Technical Lead
$168K - $241K/yr
Responsible for system and board level specification, schematic capture, FPGA design, ASIC/System ... Bachelor's degree in Electrical Engineering or Computer Engineering or Telecommunications and 8+ ...
Hardware Design Engineer Technical Lead
$168K - $241K/yr
Responsible for system and board level specification, schematic capture, FPGA design, ASIC/System ... Bachelor's degree in Electrical Engineering or Computer Engineering or Telecommunications and 8+ ...
Meta is hiring ASIC EDA Infrastructure Engineers within our Infrastructure ASIC organization. We are looking for individuals with experience in EDA flow.
Meta is hiring ASIC EDA Infrastructure Engineers within our Infrastructure ASIC organization. We are looking for individuals with experience in EDA flow.
All of this is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration ...
All of this is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration ...
All of this is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration ...
All of this is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration ...
All of this is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration ...
All of this is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration ...
Digital Verification Engineer
South San Francisco, CA · On-site
$131K - $243K/yr
We are looking for ASIC Design Verification Engineers with strong CPU, ASIC design and verification ... Experience working on complex digital systems from architecture, microarchitecture, RTL ...
Digital Verification Engineer
South San Francisco, CA · On-site
$131K - $243K/yr
We are looking for ASIC Design Verification Engineers with strong CPU, ASIC design and verification ... Experience working on complex digital systems from architecture, microarchitecture, RTL ...
Mixed-Signal Verification Engineer
San Francisco, CA · On-site
$160K - $195K/yr
All of which is driven by a world-class vertically integrated engineering team, spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration ...
Mixed-Signal Verification Engineer
San Francisco, CA · On-site
$160K - $195K/yr
All of which is driven by a world-class vertically integrated engineering team, spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration ...
Mixed-Signal Verification Engineer
San Francisco, CA · On-site
$160K - $195K/yr
All of which is driven by a world-class vertically integrated engineering team, spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration ...
Mixed-Signal Verification Engineer
San Francisco, CA · On-site
$160K - $195K/yr
All of which is driven by a world-class vertically integrated engineering team, spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration ...
Mixed-Signal Verification Engineer
San Francisco, CA · On-site
$160K - $195K/yr
All of which is driven by a world-class vertically integrated engineering team, spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration ...
Mixed-Signal Verification Engineer
San Francisco, CA · On-site
$160K - $195K/yr
All of which is driven by a world-class vertically integrated engineering team, spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration ...
FPGA Hardware Engineer
San Francisco, CA · On-site
$154K - $225K/yr
We design the networking hardware for Enterprises and Service Providers of various sizes, the ... FPGA or ASIC development experience from specification to production. * Experience with Verilog ...
FPGA Hardware Engineer
San Francisco, CA · On-site
$154K - $225K/yr
We design the networking hardware for Enterprises and Service Providers of various sizes, the ... FPGA or ASIC development experience from specification to production. * Experience with Verilog ...
Senior Silicon Physical Design Engineer - TeraWave
San Francisco, CA · On-site
$197.53 - $276.54/hr
Senior Silicon Physical Design and Layout Engineer We are seeking a Senior Silicon Physical Design ... Utilize data analytics to optimize ASIC performance and drive innovation * Work with semiconductor ...
Senior Silicon Physical Design Engineer - TeraWave
San Francisco, CA · On-site
$197.53 - $276.54/hr
Senior Silicon Physical Design and Layout Engineer We are seeking a Senior Silicon Physical Design ... Utilize data analytics to optimize ASIC performance and drive innovation * Work with semiconductor ...
We're looking for hardware engineers with hands-on experience in chip design workflows--ideally ... SPECIALTY: DI (Design Integration, RTL, Architecture) * Proven track record of developing ...
Quick apply
We're looking for hardware engineers with hands-on experience in chip design workflows--ideally ... SPECIALTY: DI (Design Integration, RTL, Architecture) * Proven track record of developing ...
Sr. RTL Verification Engineer
Redwood City, CA · On-site
$166K - $203K/yr
We are seeking a Sr. RTL Verification Engineer to join our team in Redwood City to bring the power of generative AI to enhance and speed the design and manufacture of complex semiconductors.
Sr. RTL Verification Engineer
Redwood City, CA · On-site
$166K - $203K/yr
We are seeking a Sr. RTL Verification Engineer to join our team in Redwood City to bring the power of generative AI to enhance and speed the design and manufacture of complex semiconductors.
... and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. Description In this highly visible role, you will be at the center of a ...
... and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. Description In this highly visible role, you will be at the center of a ...
... and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. Description In this highly visible role, you will be at the center of a ...
... and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. Description In this highly visible role, you will be at the center of a ...
PD - Principal, Physical Design
San Francisco, CA · On-site
$140 - $170/hr
As an Eliyan Principal Physical Design Engineer, you will be working at a fast-paced early-stage ... You will drive the development of cutting‑edge ASICs from RTL to GDSII. You will work with a ...
PD - Principal, Physical Design
San Francisco, CA · On-site
$140 - $170/hr
As an Eliyan Principal Physical Design Engineer, you will be working at a fast-paced early-stage ... You will drive the development of cutting‑edge ASICs from RTL to GDSII. You will work with a ...
Software Engineer, ASIC
South San Francisco, CA · On-site
$199K/yr
As a Software Engineer, ASIC, you will integrate tightly with teams across the company, and span ... Build and maintain scalable EDA compute infrastructure for analog and digital chip design * Develop ...
Software Engineer, ASIC
South San Francisco, CA · On-site
$199K/yr
As a Software Engineer, ASIC, you will integrate tightly with teams across the company, and span ... Build and maintain scalable EDA compute infrastructure for analog and digital chip design * Develop ...
Staff SoC RTL Engineer
Burlingame, CA · On-site
$175K - $230K/yr
As a Staff SoC RTL Engineer , you will get in on the ground floor as a key member of our chip ... Minimum 5+ years of hands-on SoC/ASIC front-end design and integration experience. * Proficiency in ...
Staff SoC RTL Engineer
Burlingame, CA · On-site
$175K - $230K/yr
As a Staff SoC RTL Engineer , you will get in on the ground floor as a key member of our chip ... Minimum 5+ years of hands-on SoC/ASIC front-end design and integration experience. * Proficiency in ...
Contractual Asic Rtl Design Engineer information
See Berkeley, CA salary details
$115.1K - $127.1K
16% of jobs
$127.1K - $139.1K
3% of jobs
$139.1K - $151.2K
4% of jobs
$154.7K is the 25th percentile. Wages below this are outliers.
$151.2K - $163.2K
6% of jobs
The median wage is $170.7K / yr.
$163.2K - $175.2K
33% of jobs
$175.2K - $187.2K
3% of jobs
$187.2K - $199.2K
2% of jobs
$207.2K is the 75th percentile. Wages above this are outliers.
$199.2K - $211.3K
12% of jobs
$211.3K - $223.3K
5% of jobs
$223.3K - $235.3K
4% of jobs
$235.3K - $247.3K
12% of jobs
$115.1K
$183.9K
$247.3K
How much do contractual asic rtl design engineer jobs pay per year?
What is the difference between Contractual Asic Rtl Design Engineer vs Digital IC Design Engineer?
| Aspect | Contractual Asic Rtl Design Engineer | Digital IC Design Engineer |
|---|---|---|
| Credentials | Bachelor's/Master's in Electrical Engineering or Computer Engineering | Bachelor's/Master's in Electrical Engineering or Computer Engineering |
| Work Environment | Contract-based, project-specific, often in semiconductor or tech companies | Full-time or contract, working on digital integrated circuit design |
| Industry Usage | Common in semiconductor, electronics, and tech firms for ASIC development | Used across semiconductor, consumer electronics, and communication industries |
Both roles require similar educational backgrounds and work in related environments, focusing on digital circuit design. The main difference is that Contractual Asic Rtl Design Engineers typically work on specific ASIC projects on a contractual basis, while Digital IC Design Engineers may have broader responsibilities in digital chip development, often in full-time roles.
What are the most commonly searched types of Asic Rtl Design Engineer jobs in Berkeley, CA?
The most popular types of Asic Rtl Design Engineer jobs in Berkeley, CA are:
What are popular job titles related to Contractual Asic Rtl Design Engineer jobs in Berkeley, CA?
For Contractual Asic Rtl Design Engineer jobs in Berkeley, CA, the most frequently searched job titles are:
What job categories do people searching Contractual Asic Rtl Design Engineer jobs in Berkeley, CA look for?
The top searched job categories for Contractual Asic Rtl Design Engineer jobs in Berkeley, CA are:
What cities near Berkeley, CA are hiring for Contractual Asic Rtl Design Engineer jobs?
Cities near Berkeley, CA with the most Contractual Asic Rtl Design Engineer job openings:

Job description
Neuralink is creating devices that enable a bi-directional interface with the brain, aiming to restore movement and sight while revolutionizing human interaction with the digital world. The Software Engineer, ASIC will integrate with teams across the company to build and maintain scalable EDA compute infrastructure and enhance developer experience for IC design and firmware engineers.
Responsibilities:
• Build and maintain scalable EDA compute infrastructure for analog and digital chip design
• Develop distributed simulation clusters to accelerate circuit verification at scale
• Manage and optimize license infrastructure across multiple EDA vendors
• Architect high-performance and robust shared storage for terabyte-scale design data
• Develop build-system infrastructure and tooling for firmware targeting custom ASICs
• Automate bare-metal server provisioning and lifecycle management for EDA compute fleets
• Enhance developer experience for IC design and firmware engineers through monitoring, self-service tooling, and robust automation
Qualifications:
Required:
• Experience administering EDA compute environments and toolchains (Cadence, Synopsys, Siemens/Mentor)
• Working knowledge of FlexLM license server administration and capacity management.
• Working knowledge of compiled languages, ideally Rust, Go, or C/C++.
• Experience with high-performance Linux storage: NFS, ZFS, Ceph, iSCSI, or similar.
• Systems administration experience on RHEL and Ubuntu, kernel tuning for compute workloads
• Familiarity with distributed compute frameworks (Ray, Slurm, LSF, or similar)
• Experience with bare-metal provisioning and lifecycle management at datacenter scale
• Familiarity with embedded cross-compilation toolchains and build systems (ARM, Bazel, Nix)
• Experience with multi-cloud deployments and hybrid on-prem/cloud architectures
• Bachelor's degree in computer science, a related field, or an equivalent combination of education, training, and/or experience
Company:
Neuralink is a neurotechnology company that focuses on developing brain-computer interfaces designed to treat neurological disorders. Founded in 2016, the company is headquartered in Fremont, USA, with a team of 201-500 employees. The company is currently Growth Stage.
About NEURALINK
Sourced by ZipRecruiter
Industry
Biotechnology research and development
Company size
201 - 500 Employees
Headquarters location
San Francisco, CA, US
Year founded
2016