... RTL Design and DV teams within Apple's HWTech organization. This role leverages advanced ... ASIC workflows Experience working directly with design and verification engineers to define ...
... RTL Design and DV teams within Apple's HWTech organization. This role leverages advanced ... ASIC workflows Experience working directly with design and verification engineers to define ...
As a Research Engineer, you'll advance our models' ability to design silicon. Hardware design is ... Have expertise in ASIC or FPGA design: RTL, design verification (UVM, formal methods, coverage ...
As a Research Engineer, you'll advance our models' ability to design silicon. Hardware design is ... Have expertise in ASIC or FPGA design: RTL, design verification (UVM, formal methods, coverage ...
Physical Design Engineer
San Francisco, CA · On-site
$130 - $170/hr
We're looking for physical design engineers to help manage and execute the physical design process ... Ability to understand what PPA limiters are from RTL and coordinate with microarchitects to change ...
Physical Design Engineer
San Francisco, CA · On-site
$130 - $170/hr
We're looking for physical design engineers to help manage and execute the physical design process ... Ability to understand what PPA limiters are from RTL and coordinate with microarchitects to change ...
Hardware Design Engineer
San Francisco, CA · On-site
$180K - $250K/yr
We're looking for a seasoned RTL design expert with over 5 years of hands-on experience, including successful tape-outs of multiple chips. Your expertise will drive the creation of advanced RL ...
Quick apply
Hardware Design Engineer
San Francisco, CA · On-site
$180K - $250K/yr
We're looking for a seasoned RTL design expert with over 5 years of hands-on experience, including successful tape-outs of multiple chips. Your expertise will drive the creation of advanced RL ...
Connectivity Systems Engineer
San Francisco, CA · On-site
$117K - $161K/yr
All of this is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration ...
Connectivity Systems Engineer
San Francisco, CA · On-site
$117K - $161K/yr
All of this is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration ...
Connectivity Systems Engineer
San Francisco, CA · On-site
$117K - $161K/yr
All of this is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration ...
Connectivity Systems Engineer
San Francisco, CA · On-site
$117K - $161K/yr
All of this is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration ...
Physical Design Engineer
San Francisco, CA · On-site
$160K - $164K/yr
Description As a Physical Design engineer you will contribute to all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII. Minimum Qualifications Bachelors ...
Physical Design Engineer
San Francisco, CA · On-site
$160K - $164K/yr
Description As a Physical Design engineer you will contribute to all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII. Minimum Qualifications Bachelors ...
We have crafted a team of exceptional engineers whose mission is to push the frontiers of what is ... Micro-architecture design and RTL implementation of: * Low-power digital signal processors * Low ...
We have crafted a team of exceptional engineers whose mission is to push the frontiers of what is ... Micro-architecture design and RTL implementation of: * Low-power digital signal processors * Low ...
Digital Verification Engineer
$163K - $199K/yr
& Responsibilities: We are looking for ASIC Design Verification Engineers with strong CPU, ASIC ... Experience working on complex digital systems from architecture, microarchitecture, RTL ...
Digital Verification Engineer
$163K - $199K/yr
& Responsibilities: We are looking for ASIC Design Verification Engineers with strong CPU, ASIC ... Experience working on complex digital systems from architecture, microarchitecture, RTL ...
Physical Design Engineer
San Francisco, CA · On-site
$160K - $164K/yr
Description As a Physical Design engineer you will contribute to all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII. Your responsibilities include ...
Physical Design Engineer
San Francisco, CA · On-site
$160K - $164K/yr
Description As a Physical Design engineer you will contribute to all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII. Your responsibilities include ...
Physical Design Engineer
San Francisco, CA · On-site
$160K - $164K/yr
Description As a Physical Design engineer you will contribute to all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII. Your responsibilities include ...
Physical Design Engineer
San Francisco, CA · On-site
$160K - $164K/yr
Description As a Physical Design engineer you will contribute to all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII. Your responsibilities include ...
Principal Compute Architect
San Francisco, CA · On-site
$180K - $300K/yr
... with RTL design (Verilog/VHDL/SystemVerilog), simulation, synthesis tools, and ASIC/FPGA ... S. or Ph.D. in Electrical Engineering, Computer Engineering, or a related field. * 8+ years of ...
Principal Compute Architect
San Francisco, CA · On-site
$180K - $300K/yr
... with RTL design (Verilog/VHDL/SystemVerilog), simulation, synthesis tools, and ASIC/FPGA ... S. or Ph.D. in Electrical Engineering, Computer Engineering, or a related field. * 8+ years of ...
Digital IC Design Engineer Intern
South San Francisco, CA · On-site
$35/hr
As a Digital IC Design Engineer Intern, your responsibilities will include ... Micro-architecture design and RTL implementation of: * Low-power digital signal processors * Low ...
Digital IC Design Engineer Intern
South San Francisco, CA · On-site
$35/hr
As a Digital IC Design Engineer Intern, your responsibilities will include ... Micro-architecture design and RTL implementation of: * Low-power digital signal processors * Low ...
Physical Design Engineer
San Francisco, CA · On-site
$160K - $164K/yr
Description As a Physical Design engineer you will contribute to all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII. Your responsibilities include ...
Physical Design Engineer
San Francisco, CA · On-site
$160K - $164K/yr
Description As a Physical Design engineer you will contribute to all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII. Your responsibilities include ...
As an ASIC Engineer specializing in architecture, performance and modeling, you will define and ... Collaborate with cross functional teams working on RTL design, Design Verification, Firmware ...
As an ASIC Engineer specializing in architecture, performance and modeling, you will define and ... Collaborate with cross functional teams working on RTL design, Design Verification, Firmware ...
MMIC Design Engineer
Menlo Park, CA · On-site +1
$160K - $250K/yr
We are seeking a highly experienced THz IC Design Engineer to join our growing team. In this role ... Understanding tradeoff at the device level for high performance ASIC implementation * Ability to ...
MMIC Design Engineer
Menlo Park, CA · On-site +1
$160K - $250K/yr
We are seeking a highly experienced THz IC Design Engineer to join our growing team. In this role ... Understanding tradeoff at the device level for high performance ASIC implementation * Ability to ...
MMIC Design Engineer
Menlo Park, CA · On-site +1
We are seeking a highly experienced THz IC Design Engineer to join our growing team. In this role ... Understanding tradeoff at the device level for high performance ASIC implementation * Ability to ...
MMIC Design Engineer
Menlo Park, CA · On-site +1
We are seeking a highly experienced THz IC Design Engineer to join our growing team. In this role ... Understanding tradeoff at the device level for high performance ASIC implementation * Ability to ...
Sr. FPGA Design & Verification Engineer
San Francisco, CA · On-site
$144K - $199K/yr
Design, implement, and verify RTL solutions using VHDL, Verilog, and SystemVerilog for FPGA IP blocks and subsystem-level functionality. * Develop, enhance, and execute functional testbenches to ...
New
Sr. FPGA Design & Verification Engineer
San Francisco, CA · On-site
$144K - $199K/yr
Design, implement, and verify RTL solutions using VHDL, Verilog, and SystemVerilog for FPGA IP blocks and subsystem-level functionality. * Develop, enhance, and execute functional testbenches to ...
New
Sr. FPGA Design & Verification Engineer
San Francisco, CA · On-site
$144K - $199K/yr
Design, implement, and verify RTL solutions using VHDL, Verilog, and SystemVerilog for FPGA IP blocks and subsystem-level functionality. * Develop, enhance, and execute functional testbenches to ...
New
Sr. FPGA Design & Verification Engineer
San Francisco, CA · On-site
$144K - $199K/yr
Design, implement, and verify RTL solutions using VHDL, Verilog, and SystemVerilog for FPGA IP blocks and subsystem-level functionality. * Develop, enhance, and execute functional testbenches to ...
New
Research Engineer, Chip Design RL (Reinforcement Learning)
San Francisco, CA · On-site
$500K - $850K/yr
Have expertise in ASIC or FPGA design: RTL, design verification (UVM, formal methods, coverage ... Know how to balance research exploration with engineering implementation. * Are passionate about AI ...
Research Engineer, Chip Design RL (Reinforcement Learning)
San Francisco, CA · On-site
$500K - $850K/yr
Have expertise in ASIC or FPGA design: RTL, design verification (UVM, formal methods, coverage ... Know how to balance research exploration with engineering implementation. * Are passionate about AI ...
Contractual Asic Rtl Design Engineer information
See Berkeley, CA salary details
$115.1K - $127.1K
16% of jobs
$127.1K - $139.1K
3% of jobs
$139.1K - $151.2K
4% of jobs
$154.7K is the 25th percentile. Wages below this are outliers.
$151.2K - $163.2K
6% of jobs
The median wage is $170.7K / yr.
$163.2K - $175.2K
33% of jobs
$175.2K - $187.2K
3% of jobs
$187.2K - $199.2K
2% of jobs
$207.2K is the 75th percentile. Wages above this are outliers.
$199.2K - $211.3K
12% of jobs
$211.3K - $223.3K
5% of jobs
$223.3K - $235.3K
4% of jobs
$235.3K - $247.3K
12% of jobs
$115.1K
$183.9K
$247.3K
How much do contractual asic rtl design engineer jobs pay per year?
What is the difference between Contractual Asic Rtl Design Engineer vs Digital IC Design Engineer?
| Aspect | Contractual Asic Rtl Design Engineer | Digital IC Design Engineer |
|---|---|---|
| Credentials | Bachelor's/Master's in Electrical Engineering or Computer Engineering | Bachelor's/Master's in Electrical Engineering or Computer Engineering |
| Work Environment | Contract-based, project-specific, often in semiconductor or tech companies | Full-time or contract, working on digital integrated circuit design |
| Industry Usage | Common in semiconductor, electronics, and tech firms for ASIC development | Used across semiconductor, consumer electronics, and communication industries |
Both roles require similar educational backgrounds and work in related environments, focusing on digital circuit design. The main difference is that Contractual Asic Rtl Design Engineers typically work on specific ASIC projects on a contractual basis, while Digital IC Design Engineers may have broader responsibilities in digital chip development, often in full-time roles.
What are the most commonly searched types of Asic Rtl Design Engineer jobs in Berkeley, CA?
The most popular types of Asic Rtl Design Engineer jobs in Berkeley, CA are:
What are popular job titles related to Contractual Asic Rtl Design Engineer jobs in Berkeley, CA?
For Contractual Asic Rtl Design Engineer jobs in Berkeley, CA, the most frequently searched job titles are:
What job categories do people searching Contractual Asic Rtl Design Engineer jobs in Berkeley, CA look for?
The top searched job categories for Contractual Asic Rtl Design Engineer jobs in Berkeley, CA are:
What cities near Berkeley, CA are hiring for Contractual Asic Rtl Design Engineer jobs?
Cities near Berkeley, CA with the most Contractual Asic Rtl Design Engineer job openings:

Other
Re-posted 15 days ago
Apple rating
8.0
Based on 677 frontline employees who took The Breakroom Quiz
7th of 30 rated technology retailers
Job description
Description
The Front-End CAD Methodology Engineer plays a key role in promoting and driving robust, scalable methodology solutions across RTL Design and DV teams within Apple's HWTech organization. This role leverages advanced automations and GenAI-driven capabilities to enhance engineering productivity, improve methodology quality, and enable intelligent workflow optimization across static verification, formal verification, simulation and emulation domains.
This position requires a combination of deep technical expertise, architectural vision, and technical leadership to identify high-impact opportunities, design and architect innovative solutions, including GenAI-enabled tooling, and drive adoption across a large globally distributed engineering organization. You will work closely with the different design organizations and CAD teams to translate complex engineering challenges into scalable, reusable, and forward-looking methodology solutions that accelerate silicon development and verification while maintaining the highest standards of quality and efficiency.
In short, this position focuses in fostering our North Star and making sure that our vision statement extends across the different design groups:
To create, monitor, and maintain high quality flows that enable Apple Silicon to produce chips that enable Apple's best products.
You will be working with an energized and highly motivated CAD team that comprehensively supports Apple's chip design efforts.
Minimum Qualifications
Minimum of BS degree and 15+ years of relevant experience
Experience with Front-End ASIC workflows
Experience working directly with design and verification engineers to define requirements and implement solutions
Experience with artificial intelligence and machine learning
Preferred Qualifications
Experience debugging vendor tool problems
Experience with Cadence or Synopsys' static/formal/dynamic verification tools
Experience with Python, TCL or Perl
Experience with JSON or YAML
Knowledge in Verilog and SystemVerilog; familiarity with VHDL
Demonstrated experience driving large-scale software system development from specification to deployment
Experience in implementing new functionality to solve emerging problems or to optimize already existing methods
Great teammate with strong written and verbal interpersonal skills, and a service and support mentality
Good communications skills are required and prior customer support experience
MSEE/CE/CS preferred
About Apple
Sourced by ZipRecruiter
Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it.
Industry
Computer and electronic product manufacturing
Company size
10,000+ Employees
Headquarters location
Cupertino, CA, US
Year founded
1976