Rtl Design Engineer Jobs in Berkeley, CA (NOW HIRING)

ASIC/SoC RTL Design Engineer Location: Palo Alto, CA (Or potentially Burlington, MA) Length of Contract: 6 months+ (Temp-to-Perm) Ideal Start: 6/1/2026 Responsibilities : Own end-to-end design of ...

... RTL, determine probably source of failures, write bug reports Work with IP vendors and Design ... engineers to resolve bugs Desired Skills and Experience Expertise in ASIC or FPGA RTL design ...

... engineering role with broad technical ownership. You will drive design from requirements through the full silicon lifecycle, from architecture definition and performance analysis through RTL ...

... RTL implementation, verification closure, physical design convergence, bring‑up, and production readiness. You will plan and oversee the work of junior engineers and help drive and develop ...

We're looking for physical design engineers to help manage and execute the physical design process ... Ability to understand what PPA limiters are from RTL and coordinate with microarchitects to change ...

We're looking for a seasoned RTL design expert with over 5 years of hands-on experience, including successful tape-outs of multiple chips. Your expertise will drive the creation of advanced RL ...

As a Wireless Design Verification Engineer, you will be responsible for pre-silicon RTL verification of wireless MAC and its interfaces with the rest of the wireless SoC. You will interact with DV ...

As a Wireless Design Verification Engineer, you will be responsible for pre-silicon RTL verification of wireless MAC and its interfaces with the rest of the wireless SoC. You will interact with DV ...

As a PHY Design Verification Engineer, you will be responsible for pre-silicon RTL verification of wireless PHY and its interfaces with the rest of the wireless communication SoC. You will interact ...

As a PHY Design Verification Engineer, you will be responsible for pre-silicon RTL verification of wireless PHY and its interfaces with the rest of the wireless communication SoC. You will interact ...

Design and implement RTL for components of a neural network accelerator * Translate architectural specifications into efficient, maintainable hardware implementations * Collaborate with hardware ...

All of this is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration ...

Description As a Physical Design engineer you will contribute to all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII. Minimum Qualifications Bachelors ...

We have crafted a team of exceptional engineers whose mission is to push the frontiers of what is ... Micro-architecture design and RTL implementation of: * Low-power digital signal processors * Low ...

Description As a Physical Design engineer you will contribute to all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII. Your responsibilities include ...

Description As a Physical Design engineer you will contribute to all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII. Your responsibilities include ...

As a Digital IC Design Engineer Intern, your responsibilities will include ... Micro-architecture design and RTL implementation of: * Low-power digital signal processors * Low ...

Compiler Developers: We compile ASIC RTL down to deterministic, FPGA-friendly emulation RTL using a ... Build debug tools to help users co-design and debug novel RISC-V hardware and software. Your ...

ASIC Design Engineer Responsibilities: * Define and bring up FPGA platforms for pre-silicon ... Map ASIC RTL to FGPA while minimizing code base differences * Create and execute test plans for ...

Description As a Physical Design engineer you will contribute to all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII. Your responsibilities include ...